mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 12:05:10 +07:00
39dd0f234f
If a PM domain is powered off when the first device starts its system PM prepare phase, genpd prevents any further attempts to power on the PM domain during the following system PM phases. Not until the system PM complete phase is finalized for all devices in the PM domain, genpd again allows it to be powered on. This behaviour needs to be changed, as a subsystem/driver for a device in the same PM domain may still need to be able to serve requests in some of the system PM phases. Accordingly, it may need to runtime resume its device and thus also request the corresponding PM domain to be powered on. To deal with these scenarios, let's make the device operational in the system PM prepare phase by runtime resuming it, no matter if the PM domain is powered on or off. Changing this also enables us to remove genpd's suspend_power_off flag, as it's being used to track this condition. Additionally, we must allow the PM domain to be powered on via runtime PM during the system PM phases. This change also requires a fix in the AMD ACP (Audio CoProcessor) drm driver. It registers a genpd to model the ACP as a PM domain, but unfortunately it's also abuses genpd's "internal" suspend_power_off flag to deal with a corner case at system PM resume. More precisely, the so called SMU block powers on the ACP at system PM resume, unconditionally if it's being used or not. This may lead to that genpd's internal status of the power state, may not correctly reflect the power state of the HW after a system PM resume. Because of changing the behaviour of genpd, by runtime resuming devices in the prepare phase, the AMD ACP drm driver no longer have to deal with this corner case. So let's just drop the related code in this driver. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Kevin Hilman <khilman@baylibre.com> Acked-by: Maruthi Bayyavarapu <maruthi.bayyavarapu@amd.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
475 lines
12 KiB
C
475 lines
12 KiB
C
/*
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* Copyright 2015 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/irqdomain.h>
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#include <linux/pm_domain.h>
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#include <linux/platform_device.h>
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#include <sound/designware_i2s.h>
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#include <sound/pcm.h>
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#include "amdgpu.h"
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#include "atom.h"
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#include "amdgpu_acp.h"
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#include "acp_gfx_if.h"
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#define ACP_TILE_ON_MASK 0x03
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#define ACP_TILE_OFF_MASK 0x02
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#define ACP_TILE_ON_RETAIN_REG_MASK 0x1f
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#define ACP_TILE_OFF_RETAIN_REG_MASK 0x20
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#define ACP_TILE_P1_MASK 0x3e
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#define ACP_TILE_P2_MASK 0x3d
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#define ACP_TILE_DSP0_MASK 0x3b
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#define ACP_TILE_DSP1_MASK 0x37
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#define ACP_TILE_DSP2_MASK 0x2f
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#define ACP_DMA_REGS_END 0x146c0
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#define ACP_I2S_PLAY_REGS_START 0x14840
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#define ACP_I2S_PLAY_REGS_END 0x148b4
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#define ACP_I2S_CAP_REGS_START 0x148b8
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#define ACP_I2S_CAP_REGS_END 0x1496c
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#define ACP_I2S_COMP1_CAP_REG_OFFSET 0xac
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#define ACP_I2S_COMP2_CAP_REG_OFFSET 0xa8
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#define ACP_I2S_COMP1_PLAY_REG_OFFSET 0x6c
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#define ACP_I2S_COMP2_PLAY_REG_OFFSET 0x68
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#define mmACP_PGFSM_RETAIN_REG 0x51c9
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#define mmACP_PGFSM_CONFIG_REG 0x51ca
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#define mmACP_PGFSM_READ_REG_0 0x51cc
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#define mmACP_MEM_SHUT_DOWN_REQ_LO 0x51f8
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#define mmACP_MEM_SHUT_DOWN_REQ_HI 0x51f9
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#define mmACP_MEM_SHUT_DOWN_STS_LO 0x51fa
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#define mmACP_MEM_SHUT_DOWN_STS_HI 0x51fb
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#define ACP_TIMEOUT_LOOP 0x000000FF
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#define ACP_DEVS 3
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#define ACP_SRC_ID 162
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enum {
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ACP_TILE_P1 = 0,
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ACP_TILE_P2,
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ACP_TILE_DSP0,
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ACP_TILE_DSP1,
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ACP_TILE_DSP2,
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};
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static int acp_sw_init(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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adev->acp.parent = adev->dev;
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adev->acp.cgs_device =
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amdgpu_cgs_create_device(adev);
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if (!adev->acp.cgs_device)
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return -EINVAL;
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return 0;
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}
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static int acp_sw_fini(void *handle)
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{
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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if (adev->acp.cgs_device)
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amdgpu_cgs_destroy_device(adev->acp.cgs_device);
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return 0;
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}
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/* power off a tile/block within ACP */
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static int acp_suspend_tile(void *cgs_dev, int tile)
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{
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u32 val = 0;
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u32 count = 0;
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if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
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pr_err("Invalid ACP tile : %d to suspend\n", tile);
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return -1;
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}
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val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
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val &= ACP_TILE_ON_MASK;
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if (val == 0x0) {
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val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
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val = val | (1 << tile);
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cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
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cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
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0x500 + tile);
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count = ACP_TIMEOUT_LOOP;
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while (true) {
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val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
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+ tile);
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val = val & ACP_TILE_ON_MASK;
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if (val == ACP_TILE_OFF_MASK)
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break;
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if (--count == 0) {
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pr_err("Timeout reading ACP PGFSM status\n");
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return -ETIMEDOUT;
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}
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udelay(100);
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}
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val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
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val |= ACP_TILE_OFF_RETAIN_REG_MASK;
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cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
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}
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return 0;
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}
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/* power on a tile/block within ACP */
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static int acp_resume_tile(void *cgs_dev, int tile)
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{
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u32 val = 0;
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u32 count = 0;
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if ((tile < ACP_TILE_P1) || (tile > ACP_TILE_DSP2)) {
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pr_err("Invalid ACP tile to resume\n");
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return -1;
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}
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val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0 + tile);
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val = val & ACP_TILE_ON_MASK;
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if (val != 0x0) {
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cgs_write_register(cgs_dev, mmACP_PGFSM_CONFIG_REG,
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0x600 + tile);
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count = ACP_TIMEOUT_LOOP;
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while (true) {
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val = cgs_read_register(cgs_dev, mmACP_PGFSM_READ_REG_0
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+ tile);
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val = val & ACP_TILE_ON_MASK;
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if (val == 0x0)
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break;
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if (--count == 0) {
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pr_err("Timeout reading ACP PGFSM status\n");
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return -ETIMEDOUT;
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}
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udelay(100);
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}
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val = cgs_read_register(cgs_dev, mmACP_PGFSM_RETAIN_REG);
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if (tile == ACP_TILE_P1)
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val = val & (ACP_TILE_P1_MASK);
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else if (tile == ACP_TILE_P2)
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val = val & (ACP_TILE_P2_MASK);
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cgs_write_register(cgs_dev, mmACP_PGFSM_RETAIN_REG, val);
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}
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return 0;
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}
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struct acp_pm_domain {
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void *cgs_dev;
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struct generic_pm_domain gpd;
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};
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static int acp_poweroff(struct generic_pm_domain *genpd)
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{
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int i, ret;
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struct acp_pm_domain *apd;
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apd = container_of(genpd, struct acp_pm_domain, gpd);
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if (apd != NULL) {
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/* Donot return abruptly if any of power tile fails to suspend.
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* Log it and continue powering off other tile
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*/
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for (i = 4; i >= 0 ; i--) {
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ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_P1 + i);
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if (ret)
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pr_err("ACP tile %d tile suspend failed\n", i);
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}
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}
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return 0;
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}
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static int acp_poweron(struct generic_pm_domain *genpd)
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{
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int i, ret;
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struct acp_pm_domain *apd;
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apd = container_of(genpd, struct acp_pm_domain, gpd);
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if (apd != NULL) {
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for (i = 0; i < 2; i++) {
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ret = acp_resume_tile(apd->cgs_dev, ACP_TILE_P1 + i);
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if (ret) {
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pr_err("ACP tile %d resume failed\n", i);
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break;
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}
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}
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/* Disable DSPs which are not going to be used */
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for (i = 0; i < 3; i++) {
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ret = acp_suspend_tile(apd->cgs_dev, ACP_TILE_DSP0 + i);
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/* Continue suspending other DSP, even if one fails */
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if (ret)
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pr_err("ACP DSP %d suspend failed\n", i);
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}
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}
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return 0;
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}
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static struct device *get_mfd_cell_dev(const char *device_name, int r)
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{
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char auto_dev_name[25];
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struct device *dev;
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snprintf(auto_dev_name, sizeof(auto_dev_name),
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"%s.%d.auto", device_name, r);
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dev = bus_find_device_by_name(&platform_bus_type, NULL, auto_dev_name);
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dev_info(dev, "device %s added to pm domain\n", auto_dev_name);
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return dev;
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}
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/**
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* acp_hw_init - start and test ACP block
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*
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* @adev: amdgpu_device pointer
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*
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*/
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static int acp_hw_init(void *handle)
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{
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int r, i;
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uint64_t acp_base;
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struct device *dev;
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struct i2s_platform_data *i2s_pdata;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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const struct amdgpu_ip_block_version *ip_version =
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amdgpu_get_ip_block(adev, AMD_IP_BLOCK_TYPE_ACP);
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if (!ip_version)
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return -EINVAL;
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r = amd_acp_hw_init(adev->acp.cgs_device,
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ip_version->major, ip_version->minor);
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/* -ENODEV means board uses AZ rather than ACP */
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if (r == -ENODEV)
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return 0;
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else if (r)
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return r;
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r = cgs_get_pci_resource(adev->acp.cgs_device, CGS_RESOURCE_TYPE_MMIO,
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0x5289, 0, &acp_base);
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if (r == -ENODEV)
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return 0;
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else if (r)
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return r;
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adev->acp.acp_genpd = kzalloc(sizeof(struct acp_pm_domain), GFP_KERNEL);
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if (adev->acp.acp_genpd == NULL)
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return -ENOMEM;
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adev->acp.acp_genpd->gpd.name = "ACP_AUDIO";
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adev->acp.acp_genpd->gpd.power_off = acp_poweroff;
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adev->acp.acp_genpd->gpd.power_on = acp_poweron;
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adev->acp.acp_genpd->cgs_dev = adev->acp.cgs_device;
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pm_genpd_init(&adev->acp.acp_genpd->gpd, NULL, false);
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adev->acp.acp_cell = kzalloc(sizeof(struct mfd_cell) * ACP_DEVS,
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GFP_KERNEL);
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if (adev->acp.acp_cell == NULL)
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return -ENOMEM;
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adev->acp.acp_res = kzalloc(sizeof(struct resource) * 4, GFP_KERNEL);
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if (adev->acp.acp_res == NULL) {
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kfree(adev->acp.acp_cell);
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return -ENOMEM;
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}
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i2s_pdata = kzalloc(sizeof(struct i2s_platform_data) * 2, GFP_KERNEL);
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if (i2s_pdata == NULL) {
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kfree(adev->acp.acp_res);
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kfree(adev->acp.acp_cell);
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return -ENOMEM;
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}
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i2s_pdata[0].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET;
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i2s_pdata[0].cap = DWC_I2S_PLAY;
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i2s_pdata[0].snd_rates = SNDRV_PCM_RATE_8000_96000;
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i2s_pdata[0].i2s_reg_comp1 = ACP_I2S_COMP1_PLAY_REG_OFFSET;
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i2s_pdata[0].i2s_reg_comp2 = ACP_I2S_COMP2_PLAY_REG_OFFSET;
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i2s_pdata[1].quirks = DW_I2S_QUIRK_COMP_REG_OFFSET |
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DW_I2S_QUIRK_COMP_PARAM1;
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i2s_pdata[1].cap = DWC_I2S_RECORD;
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i2s_pdata[1].snd_rates = SNDRV_PCM_RATE_8000_96000;
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i2s_pdata[1].i2s_reg_comp1 = ACP_I2S_COMP1_CAP_REG_OFFSET;
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i2s_pdata[1].i2s_reg_comp2 = ACP_I2S_COMP2_CAP_REG_OFFSET;
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adev->acp.acp_res[0].name = "acp2x_dma";
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adev->acp.acp_res[0].flags = IORESOURCE_MEM;
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adev->acp.acp_res[0].start = acp_base;
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adev->acp.acp_res[0].end = acp_base + ACP_DMA_REGS_END;
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adev->acp.acp_res[1].name = "acp2x_dw_i2s_play";
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adev->acp.acp_res[1].flags = IORESOURCE_MEM;
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adev->acp.acp_res[1].start = acp_base + ACP_I2S_PLAY_REGS_START;
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adev->acp.acp_res[1].end = acp_base + ACP_I2S_PLAY_REGS_END;
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adev->acp.acp_res[2].name = "acp2x_dw_i2s_cap";
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adev->acp.acp_res[2].flags = IORESOURCE_MEM;
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adev->acp.acp_res[2].start = acp_base + ACP_I2S_CAP_REGS_START;
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adev->acp.acp_res[2].end = acp_base + ACP_I2S_CAP_REGS_END;
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adev->acp.acp_res[3].name = "acp2x_dma_irq";
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adev->acp.acp_res[3].flags = IORESOURCE_IRQ;
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adev->acp.acp_res[3].start = amdgpu_irq_create_mapping(adev, 162);
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adev->acp.acp_res[3].end = adev->acp.acp_res[3].start;
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adev->acp.acp_cell[0].name = "acp_audio_dma";
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adev->acp.acp_cell[0].num_resources = 4;
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adev->acp.acp_cell[0].resources = &adev->acp.acp_res[0];
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adev->acp.acp_cell[1].name = "designware-i2s";
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adev->acp.acp_cell[1].num_resources = 1;
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adev->acp.acp_cell[1].resources = &adev->acp.acp_res[1];
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adev->acp.acp_cell[1].platform_data = &i2s_pdata[0];
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adev->acp.acp_cell[1].pdata_size = sizeof(struct i2s_platform_data);
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adev->acp.acp_cell[2].name = "designware-i2s";
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adev->acp.acp_cell[2].num_resources = 1;
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adev->acp.acp_cell[2].resources = &adev->acp.acp_res[2];
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adev->acp.acp_cell[2].platform_data = &i2s_pdata[1];
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adev->acp.acp_cell[2].pdata_size = sizeof(struct i2s_platform_data);
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r = mfd_add_hotplug_devices(adev->acp.parent, adev->acp.acp_cell,
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ACP_DEVS);
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if (r)
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return r;
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for (i = 0; i < ACP_DEVS ; i++) {
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dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
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r = pm_genpd_add_device(&adev->acp.acp_genpd->gpd, dev);
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if (r) {
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dev_err(dev, "Failed to add dev to genpd\n");
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return r;
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}
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}
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return 0;
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}
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/**
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* acp_hw_fini - stop the hardware block
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*
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* @adev: amdgpu_device pointer
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*
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*/
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static int acp_hw_fini(void *handle)
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{
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int i, ret;
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struct device *dev;
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struct amdgpu_device *adev = (struct amdgpu_device *)handle;
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for (i = 0; i < ACP_DEVS ; i++) {
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dev = get_mfd_cell_dev(adev->acp.acp_cell[i].name, i);
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ret = pm_genpd_remove_device(&adev->acp.acp_genpd->gpd, dev);
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/* If removal fails, dont giveup and try rest */
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if (ret)
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dev_err(dev, "remove dev from genpd failed\n");
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}
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mfd_remove_devices(adev->acp.parent);
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kfree(adev->acp.acp_res);
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kfree(adev->acp.acp_genpd);
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kfree(adev->acp.acp_cell);
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return 0;
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}
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static int acp_suspend(void *handle)
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|
{
|
|
return 0;
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|
}
|
|
|
|
static int acp_resume(void *handle)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int acp_early_init(void *handle)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static bool acp_is_idle(void *handle)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
static int acp_wait_for_idle(void *handle)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int acp_soft_reset(void *handle)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int acp_set_clockgating_state(void *handle,
|
|
enum amd_clockgating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int acp_set_powergating_state(void *handle,
|
|
enum amd_powergating_state state)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
const struct amd_ip_funcs acp_ip_funcs = {
|
|
.name = "acp_ip",
|
|
.early_init = acp_early_init,
|
|
.late_init = NULL,
|
|
.sw_init = acp_sw_init,
|
|
.sw_fini = acp_sw_fini,
|
|
.hw_init = acp_hw_init,
|
|
.hw_fini = acp_hw_fini,
|
|
.suspend = acp_suspend,
|
|
.resume = acp_resume,
|
|
.is_idle = acp_is_idle,
|
|
.wait_for_idle = acp_wait_for_idle,
|
|
.soft_reset = acp_soft_reset,
|
|
.set_clockgating_state = acp_set_clockgating_state,
|
|
.set_powergating_state = acp_set_powergating_state,
|
|
};
|