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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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eee3af4a2c
Resend using different mail client Changes to the last version: - split implementation into two layers: ds/bts and ptrace - renamed TIF's - save/restore ds save area msr in __switch_to_xtra() - make block-stepping only look at BTF bit Signed-off-by: Markus Metzger <markus.t.metzger@intel.com> Signed-off-by: Suresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
66 lines
1.5 KiB
C
66 lines
1.5 KiB
C
/*
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* Debug Store (DS) support
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*
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* This provides a low-level interface to the hardware's Debug Store
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* feature that is used for last branch recording (LBR) and
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* precise-event based sampling (PEBS).
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*
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* Different architectures use a different DS layout/pointer size.
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* The below functions therefore work on a void*.
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*
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*
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* Since there is no user for PEBS, yet, only LBR (or branch
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* trace store, BTS) is supported.
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*
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*
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* Copyright (C) 2007 Intel Corporation.
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* Markus Metzger <markus.t.metzger@intel.com>, Dec 2007
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*/
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#ifndef _ASM_X86_DS_H
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#define _ASM_X86_DS_H
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#include <linux/types.h>
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#include <linux/init.h>
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struct cpuinfo_x86;
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/* a branch trace record entry
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*
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* In order to unify the interface between various processor versions,
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* we use the below data structure for all processors.
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*/
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enum bts_qualifier {
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BTS_INVALID = 0,
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BTS_BRANCH,
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BTS_TASK_ARRIVES,
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BTS_TASK_DEPARTS
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};
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struct bts_struct {
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enum bts_qualifier qualifier;
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union {
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/* BTS_BRANCH */
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struct {
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long from_ip;
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long to_ip;
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} lbr;
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/* BTS_TASK_ARRIVES or
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BTS_TASK_DEPARTS */
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unsigned long long timestamp;
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} variant;
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};
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extern int ds_allocate(void **, size_t);
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extern int ds_free(void **);
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extern int ds_get_bts_size(void *);
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extern int ds_get_bts_index(void *);
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extern int ds_read_bts(void *, size_t, struct bts_struct *);
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extern int ds_write_bts(void *, const struct bts_struct *);
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extern unsigned long ds_debugctl_mask(void);
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extern void __cpuinit ds_init_intel(struct cpuinfo_x86 *c);
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#endif /* _ASM_X86_DS_H */
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