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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2b4e38fd7c
The VExpress development platform has an external expansion bus which can be used for additional hardware (e.g. LogicTile Express daughter boards). Add this bus to the VExpress CoreTile device-trees.The bus is described for a CoreTile occupying site 1. Acked-by: Liviu Dudau <Liviu.Dudau@arm.com> Signed-off-by: Brian Starkey <brian.starkey@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
376 lines
8.2 KiB
Plaintext
376 lines
8.2 KiB
Plaintext
/*
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* ARM Ltd. Versatile Express
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*
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* CoreTile Express A9x4
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* Cortex-A9 MPCore (V2P-CA9)
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*
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* HBI-0191B
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*/
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/dts-v1/;
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/ {
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model = "V2P-CA9";
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arm,hbi = <0x191>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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serial1 = &v2m_serial1;
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serial2 = &v2m_serial2;
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serial3 = &v2m_serial3;
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i2c0 = &v2m_i2c_dvi;
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i2c1 = &v2m_i2c_pcie;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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A9_0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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next-level-cache = <&L2>;
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};
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A9_1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <1>;
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next-level-cache = <&L2>;
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};
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A9_2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <2>;
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next-level-cache = <&L2>;
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};
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A9_3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <3>;
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next-level-cache = <&L2>;
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};
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};
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memory@60000000 {
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device_type = "memory";
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reg = <0x60000000 0x40000000>;
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};
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clcd@10020000 {
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compatible = "arm,pl111", "arm,primecell";
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reg = <0x10020000 0x1000>;
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interrupt-names = "combined";
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interrupts = <0 44 4>;
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clocks = <&oscclk1>, <&oscclk2>;
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clock-names = "clcdclk", "apb_pclk";
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max-memory-bandwidth = <130000000>; /* 16bpp @ 63.5MHz */
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port {
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clcd_pads: endpoint {
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remote-endpoint = <&clcd_panel>;
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arm,pl11x,tft-r0g0b0-pads = <0 8 16>;
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};
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};
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panel {
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compatible = "panel-dpi";
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port {
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clcd_panel: endpoint {
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remote-endpoint = <&clcd_pads>;
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};
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};
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panel-timing {
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clock-frequency = <63500127>;
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hactive = <1024>;
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hback-porch = <152>;
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hfront-porch = <48>;
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hsync-len = <104>;
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vactive = <768>;
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vback-porch = <23>;
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vfront-porch = <3>;
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vsync-len = <4>;
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};
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};
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};
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memory-controller@100e0000 {
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compatible = "arm,pl341", "arm,primecell";
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reg = <0x100e0000 0x1000>;
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clocks = <&oscclk2>;
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clock-names = "apb_pclk";
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};
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memory-controller@100e1000 {
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compatible = "arm,pl354", "arm,primecell";
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reg = <0x100e1000 0x1000>;
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interrupts = <0 45 4>,
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<0 46 4>;
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clocks = <&oscclk2>;
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clock-names = "apb_pclk";
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};
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timer@100e4000 {
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compatible = "arm,sp804", "arm,primecell";
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reg = <0x100e4000 0x1000>;
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interrupts = <0 48 4>,
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<0 49 4>;
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clocks = <&oscclk2>, <&oscclk2>;
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clock-names = "timclk", "apb_pclk";
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status = "disabled";
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};
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watchdog@100e5000 {
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compatible = "arm,sp805", "arm,primecell";
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reg = <0x100e5000 0x1000>;
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interrupts = <0 51 4>;
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clocks = <&oscclk2>, <&oscclk2>;
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clock-names = "wdogclk", "apb_pclk";
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};
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scu@1e000000 {
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compatible = "arm,cortex-a9-scu";
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reg = <0x1e000000 0x58>;
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};
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timer@1e000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0x1e000600 0x20>;
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interrupts = <1 13 0xf04>;
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};
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watchdog@1e000620 {
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compatible = "arm,cortex-a9-twd-wdt";
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reg = <0x1e000620 0x20>;
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interrupts = <1 14 0xf04>;
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};
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gic: interrupt-controller@1e001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x1e001000 0x1000>,
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<0x1e000100 0x100>;
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};
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L2: cache-controller@1e00a000 {
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compatible = "arm,pl310-cache";
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reg = <0x1e00a000 0x1000>;
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interrupts = <0 43 4>;
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cache-unified;
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cache-level = <2>;
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arm,data-latency = <1 1 1>;
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arm,tag-latency = <1 1 1>;
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};
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pmu {
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compatible = "arm,cortex-a9-pmu";
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interrupts = <0 60 4>,
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<0 61 4>,
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<0 62 4>,
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<0 63 4>;
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interrupt-affinity = <&A9_0>, <&A9_1>, <&A9_2>, <&A9_3>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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oscclk0: extsaxiclk {
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/* ACLK clock to the AXI master port on the test chip */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 0>;
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freq-range = <30000000 50000000>;
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#clock-cells = <0>;
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clock-output-names = "extsaxiclk";
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};
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oscclk1: clcdclk {
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/* Reference clock for the CLCD */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 1>;
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freq-range = <10000000 80000000>;
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#clock-cells = <0>;
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clock-output-names = "clcdclk";
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};
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smbclk: oscclk2: tcrefclk {
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/* Reference clock for the test chip internal PLLs */
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compatible = "arm,vexpress-osc";
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arm,vexpress-sysreg,func = <1 2>;
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freq-range = <33000000 100000000>;
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#clock-cells = <0>;
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clock-output-names = "tcrefclk";
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};
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volt-vd10 {
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/* Test Chip internal logic voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 0>;
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regulator-name = "VD10";
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regulator-always-on;
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label = "VD10";
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};
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volt-vd10-s2 {
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/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 1>;
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regulator-name = "VD10_S2";
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regulator-always-on;
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label = "VD10_S2";
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};
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volt-vd10-s3 {
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/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 2>;
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regulator-name = "VD10_S3";
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regulator-always-on;
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label = "VD10_S3";
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};
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volt-vcc1v8 {
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/* DDR2 SDRAM and Test Chip DDR2 I/O supply */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 3>;
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regulator-name = "VCC1V8";
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regulator-always-on;
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label = "VCC1V8";
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};
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volt-ddr2vtt {
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/* DDR2 SDRAM VTT termination voltage */
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compatible = "arm,vexpress-volt";
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arm,vexpress-sysreg,func = <2 4>;
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regulator-name = "DDR2VTT";
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regulator-always-on;
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label = "DDR2VTT";
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};
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volt-vcc3v3 {
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/* Local board supply for miscellaneous logic external to the Test Chip */
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arm,vexpress-sysreg,func = <2 5>;
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compatible = "arm,vexpress-volt";
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regulator-name = "VCC3V3";
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regulator-always-on;
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label = "VCC3V3";
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};
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amp-vd10-s2 {
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/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
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compatible = "arm,vexpress-amp";
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arm,vexpress-sysreg,func = <3 0>;
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label = "VD10_S2";
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};
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amp-vd10-s3 {
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/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
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compatible = "arm,vexpress-amp";
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arm,vexpress-sysreg,func = <3 1>;
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label = "VD10_S3";
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};
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power-vd10-s2 {
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/* PL310, L2 cache, RAM cell supply (not PL310 logic) */
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compatible = "arm,vexpress-power";
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arm,vexpress-sysreg,func = <12 0>;
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label = "PVD10_S2";
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};
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power-vd10-s3 {
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/* Cortex-A9 system supply, Cores, MPEs, SCU and PL310 logic */
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compatible = "arm,vexpress-power";
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arm,vexpress-sysreg,func = <12 1>;
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label = "PVD10_S3";
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};
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};
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smb@04000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <0 0 0x40000000 0x04000000>,
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<1 0 0x44000000 0x04000000>,
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<2 0 0x48000000 0x04000000>,
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<3 0 0x4c000000 0x04000000>,
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<7 0 0x10000000 0x00020000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <0 0 0 &gic 0 0 4>,
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<0 0 1 &gic 0 1 4>,
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<0 0 2 &gic 0 2 4>,
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<0 0 3 &gic 0 3 4>,
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<0 0 4 &gic 0 4 4>,
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<0 0 5 &gic 0 5 4>,
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<0 0 6 &gic 0 6 4>,
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<0 0 7 &gic 0 7 4>,
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<0 0 8 &gic 0 8 4>,
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<0 0 9 &gic 0 9 4>,
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<0 0 10 &gic 0 10 4>,
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<0 0 11 &gic 0 11 4>,
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<0 0 12 &gic 0 12 4>,
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<0 0 13 &gic 0 13 4>,
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<0 0 14 &gic 0 14 4>,
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<0 0 15 &gic 0 15 4>,
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<0 0 16 &gic 0 16 4>,
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<0 0 17 &gic 0 17 4>,
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<0 0 18 &gic 0 18 4>,
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<0 0 19 &gic 0 19 4>,
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<0 0 20 &gic 0 20 4>,
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<0 0 21 &gic 0 21 4>,
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<0 0 22 &gic 0 22 4>,
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<0 0 23 &gic 0 23 4>,
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<0 0 24 &gic 0 24 4>,
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<0 0 25 &gic 0 25 4>,
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<0 0 26 &gic 0 26 4>,
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<0 0 27 &gic 0 27 4>,
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<0 0 28 &gic 0 28 4>,
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<0 0 29 &gic 0 29 4>,
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<0 0 30 &gic 0 30 4>,
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<0 0 31 &gic 0 31 4>,
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<0 0 32 &gic 0 32 4>,
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<0 0 33 &gic 0 33 4>,
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<0 0 34 &gic 0 34 4>,
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<0 0 35 &gic 0 35 4>,
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<0 0 36 &gic 0 36 4>,
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<0 0 37 &gic 0 37 4>,
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<0 0 38 &gic 0 38 4>,
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<0 0 39 &gic 0 39 4>,
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<0 0 40 &gic 0 40 4>,
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<0 0 41 &gic 0 41 4>,
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<0 0 42 &gic 0 42 4>;
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/include/ "vexpress-v2m.dtsi"
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};
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site2: hsb@e0000000 {
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compatible = "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0xe0000000 0x20000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 3>;
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interrupt-map = <0 0 &gic 0 36 4>,
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<0 1 &gic 0 37 4>,
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<0 2 &gic 0 38 4>,
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<0 3 &gic 0 39 4>;
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};
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};
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