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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 05:35:12 +07:00
8fff2f752f
The patch
"ARM: 8432/1: move VMALLOC_END from 0xff000000 to 0xff800000"
(sha1: 6ff0966052)
has moved also start of VMALLOC area because size didn't change.
That's why origin location of vmalloc was
vmalloc : 0xf0000000 - 0xff000000 ( 240 MB)
and now is
vmalloc : 0xf0800000 - 0xff800000 ( 240 MB)
That's why uart virtual addresses need to be changed to reflect this new
memory setup. Starting address should be vmalloc start address.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
57 lines
1.6 KiB
ArmAsm
57 lines
1.6 KiB
ArmAsm
/*
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* Debugging macro include header
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*
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* Copyright (C) 2011 Xilinx
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*
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* This software is licensed under the terms of the GNU General Public
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* License version 2, as published by the Free Software Foundation, and
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* may be copied, distributed, and modified under those terms.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
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#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
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#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
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#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
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#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
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#define UART0_PHYS 0xE0000000
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#define UART0_VIRT 0xF0800000
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#define UART1_PHYS 0xE0001000
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#define UART1_VIRT 0xF0801000
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#if IS_ENABLED(CONFIG_DEBUG_ZYNQ_UART1)
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# define LL_UART_PADDR UART1_PHYS
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# define LL_UART_VADDR UART1_VIRT
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#else
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# define LL_UART_PADDR UART0_PHYS
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# define LL_UART_VADDR UART0_VIRT
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#endif
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.macro addruart, rp, rv, tmp
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ldr \rp, =LL_UART_PADDR @ physical
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ldr \rv, =LL_UART_VADDR @ virtual
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.endm
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.macro senduart,rd,rx
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strb \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
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.endm
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.macro waituart,rd,rx
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1001: ldr \rd, [\rx, #UART_SR_OFFSET]
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ARM_BE8( rev \rd, \rd )
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tst \rd, #UART_SR_TXEMPTY
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
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ARM_BE8( rev \rd, \rd )
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tst \rd, #UART_SR_TXFULL @
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bne 1002b @ wait if FIFO is full
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.endm
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