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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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d31626f70b
Currently, when we have a process using the transactional memory
facilities on POWER8 (that is, the processor is in transactional
or suspended state), and the process enters the kernel and the
kernel then uses the floating-point or vector (VMX/Altivec) facility,
we end up corrupting the user-visible FP/VMX/VSX state. This
happens, for example, if a page fault causes a copy-on-write
operation, because the copy_page function will use VMX to do the
copy on POWER8. The test program below demonstrates the bug.
The bug happens because when FP/VMX state for a transactional process
is stored in the thread_struct, we store the checkpointed state in
.fp_state/.vr_state and the transactional (current) state in
.transact_fp/.transact_vr. However, when the kernel wants to use
FP/VMX, it calls enable_kernel_fp() or enable_kernel_altivec(),
which saves the current state in .fp_state/.vr_state. Furthermore,
when we return to the user process we return with FP/VMX/VSX
disabled. The next time the process uses FP/VMX/VSX, we don't know
which set of state (the current register values, .fp_state/.vr_state,
or .transact_fp/.transact_vr) we should be using, since we have no
way to tell if we are still in the same transaction, and if not,
whether the previous transaction succeeded or failed.
Thus it is necessary to strictly adhere to the rule that if FP has
been enabled at any point in a transaction, we must keep FP enabled
for the user process with the current transactional state in the
FP registers, until we detect that it is no longer in a transaction.
Similarly for VMX; once enabled it must stay enabled until the
process is no longer transactional.
In order to keep this rule, we add a new thread_info flag which we
test when returning from the kernel to userspace, called TIF_RESTORE_TM.
This flag indicates that there is FP/VMX/VSX state to be restored
before entering userspace, and when it is set the .tm_orig_msr field
in the thread_struct indicates what state needs to be restored.
The restoration is done by restore_tm_state(). The TIF_RESTORE_TM
bit is set by new giveup_fpu/altivec_maybe_transactional helpers,
which are called from enable_kernel_fp/altivec, giveup_vsx, and
flush_fp/altivec_to_thread instead of giveup_fpu/altivec.
The other thing to be done is to get the transactional FP/VMX/VSX
state from .fp_state/.vr_state when doing reclaim, if that state
has been saved there by giveup_fpu/altivec_maybe_transactional.
Having done this, we set the FP/VMX bit in the thread's MSR after
reclaim to indicate that that part of the state is now valid
(having been reclaimed from the processor's checkpointed state).
Finally, in the signal handling code, we move the clearing of the
transactional state bits in the thread's MSR a bit earlier, before
calling flush_fp_to_thread(), so that we don't unnecessarily set
the TIF_RESTORE_TM bit.
This is the test program:
/* Michael Neuling 4/12/2013
*
* See if the altivec state is leaked out of an aborted transaction due to
* kernel vmx copy loops.
*
* gcc -m64 htm_vmxcopy.c -o htm_vmxcopy
*
*/
/* We don't use all of these, but for reference: */
int main(int argc, char *argv[])
{
long double vecin = 1.3;
long double vecout;
unsigned long pgsize = getpagesize();
int i;
int fd;
int size = pgsize*16;
char tmpfile[] = "/tmp/page_faultXXXXXX";
char buf[pgsize];
char *a;
uint64_t aborted = 0;
fd = mkstemp(tmpfile);
assert(fd >= 0);
memset(buf, 0, pgsize);
for (i = 0; i < size; i += pgsize)
assert(write(fd, buf, pgsize) == pgsize);
unlink(tmpfile);
a = mmap(NULL, size, PROT_READ|PROT_WRITE, MAP_PRIVATE, fd, 0);
assert(a != MAP_FAILED);
asm __volatile__(
"lxvd2x 40,0,%[vecinptr] ; " // set 40 to initial value
TBEGIN
"beq 3f ;"
TSUSPEND
"xxlxor 40,40,40 ; " // set 40 to 0
"std 5, 0(%[map]) ;" // cause kernel vmx copy page
TABORT
TRESUME
TEND
"li %[res], 0 ;"
"b 5f ;"
"3: ;" // Abort handler
"li %[res], 1 ;"
"5: ;"
"stxvd2x 40,0,%[vecoutptr] ; "
: [res]"=r"(aborted)
: [vecinptr]"r"(&vecin),
[vecoutptr]"r"(&vecout),
[map]"r"(a)
: "memory", "r0", "r3", "r4", "r5", "r6", "r7");
if (aborted && (vecin != vecout)){
printf("FAILED: vector state leaked on abort %f != %f\n",
(double)vecin, (double)vecout);
exit(1);
}
munmap(a, size);
close(fd);
printf("PASSED!\n");
return 0;
}
Signed-off-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
254 lines
6.2 KiB
ArmAsm
254 lines
6.2 KiB
ArmAsm
/*
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* FPU support code, moved here from head.S so that it can be used
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* by chips which use other head-whatever.S files.
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*
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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* Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
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* Copyright (C) 1996 Paul Mackerras.
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* Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <asm/reg.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/pgtable.h>
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#include <asm/cputable.h>
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#include <asm/cache.h>
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#include <asm/thread_info.h>
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#include <asm/ppc_asm.h>
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#include <asm/asm-offsets.h>
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#include <asm/ptrace.h>
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#ifdef CONFIG_VSX
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#define __REST_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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REST_32FPRS(n,base); \
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b 3f; \
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2: REST_32VSRS(n,c,base); \
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3:
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#define __SAVE_32FPVSRS(n,c,base) \
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BEGIN_FTR_SECTION \
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b 2f; \
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END_FTR_SECTION_IFSET(CPU_FTR_VSX); \
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SAVE_32FPRS(n,base); \
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b 3f; \
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2: SAVE_32VSRS(n,c,base); \
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3:
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#else
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#define __REST_32FPVSRS(n,b,base) REST_32FPRS(n, base)
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#define __SAVE_32FPVSRS(n,b,base) SAVE_32FPRS(n, base)
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#endif
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#define REST_32FPVSRS(n,c,base) __REST_32FPVSRS(n,__REG_##c,__REG_##base)
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#define SAVE_32FPVSRS(n,c,base) __SAVE_32FPVSRS(n,__REG_##c,__REG_##base)
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#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
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/* void do_load_up_transact_fpu(struct thread_struct *thread)
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*
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* This is similar to load_up_fpu but for the transactional version of the FP
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* register set. It doesn't mess with the task MSR or valid flags.
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* Furthermore, we don't do lazy FP with TM currently.
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*/
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_GLOBAL(do_load_up_transact_fpu)
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mfmsr r6
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ori r5,r6,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC
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MTMSRD(r5)
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addi r7,r3,THREAD_TRANSACT_FPSTATE
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lfd fr0,FPSTATE_FPSCR(r7)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R7)
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/* FP/VSX off again */
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MTMSRD(r6)
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SYNC
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blr
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#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
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/*
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* Enable use of the FPU, and VSX if possible, for the caller.
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*/
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_GLOBAL(fp_enable)
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mfmsr r3
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ori r3,r3,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r3,r3,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC
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MTMSRD(r3)
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isync /* (not necessary for arch 2.02 and later) */
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blr
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/*
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* Load state from memory into FP registers including FPSCR.
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(load_fp_state)
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lfd fr0,FPSTATE_FPSCR(r3)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R3)
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blr
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/*
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* Store FP state into memory, including FPSCR
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* Assumes the caller has enabled FP in the MSR.
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*/
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_GLOBAL(store_fp_state)
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SAVE_32FPVSRS(0, R4, R3)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r3)
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blr
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/*
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* This task wants to use the FPU now.
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* On UP, disable FP for the task which had the FPU previously,
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* and save its floating-point registers in its thread_struct.
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* Load up this task's FP registers from its thread_struct,
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* enable the FPU for the current task and return to the task.
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* Note that on 32-bit this can only use registers that will be
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* restored by fast_exception_return, i.e. r3 - r6, r10 and r11.
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*/
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_GLOBAL(load_up_fpu)
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mfmsr r5
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ori r5,r5,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC
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MTMSRD(r5) /* enable use of fpu now */
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isync
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/*
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* For SMP, we don't do lazy FPU switching because it just gets too
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* horrendously complex, especially when a task switches from one CPU
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* to another. Instead we call giveup_fpu in switch_to.
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*/
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#ifndef CONFIG_SMP
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LOAD_REG_ADDRBASE(r3, last_task_used_math)
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toreal(r3)
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PPC_LL r4,ADDROFF(last_task_used_math)(r3)
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PPC_LCMPI 0,r4,0
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beq 1f
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toreal(r4)
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addi r4,r4,THREAD /* want last_task_used_math->thread */
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addi r10,r4,THREAD_FPSTATE
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SAVE_32FPVSRS(0, R5, R10)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r10)
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PPC_LL r5,PT_REGS(r4)
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toreal(r5)
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PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r10,MSR_FP|MSR_FE0|MSR_FE1
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andc r4,r4,r10 /* disable FP for previous task */
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PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#endif /* CONFIG_SMP */
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/* enable use of FP after return */
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#ifdef CONFIG_PPC32
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mfspr r5,SPRN_SPRG_THREAD /* current task's THREAD (phys) */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r9,r9,MSR_FP /* enable FP for current */
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or r9,r9,r4
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#else
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ld r4,PACACURRENT(r13)
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addi r5,r4,THREAD /* Get THREAD */
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lwz r4,THREAD_FPEXC_MODE(r5)
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ori r12,r12,MSR_FP
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or r12,r12,r4
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std r12,_MSR(r1)
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#endif
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addi r10,r5,THREAD_FPSTATE
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lfd fr0,FPSTATE_FPSCR(r10)
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MTFSF_L(fr0)
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REST_32FPVSRS(0, R4, R10)
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#ifndef CONFIG_SMP
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subi r4,r5,THREAD
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fromreal(r4)
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PPC_STL r4,ADDROFF(last_task_used_math)(r3)
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#endif /* CONFIG_SMP */
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/* restore registers and return */
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/* we haven't used ctr or xer or lr */
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blr
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/*
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* giveup_fpu(tsk)
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* Disable FP for the task given as the argument,
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* and save the floating-point registers in its thread_struct.
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* Enables the FPU for use in the kernel on return.
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*/
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_GLOBAL(giveup_fpu)
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mfmsr r5
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ori r5,r5,MSR_FP
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r5,r5,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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SYNC_601
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ISYNC_601
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MTMSRD(r5) /* enable use of fpu now */
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SYNC_601
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isync
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PPC_LCMPI 0,r3,0
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beqlr- /* if no previous owner, done */
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addi r3,r3,THREAD /* want THREAD of task */
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PPC_LL r6,THREAD_FPSAVEAREA(r3)
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PPC_LL r5,PT_REGS(r3)
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PPC_LCMPI 0,r6,0
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bne 2f
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addi r6,r3,THREAD_FPSTATE
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2: PPC_LCMPI 0,r5,0
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SAVE_32FPVSRS(0, R4, R6)
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mffs fr0
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stfd fr0,FPSTATE_FPSCR(r6)
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beq 1f
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PPC_LL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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li r3,MSR_FP|MSR_FE0|MSR_FE1
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#ifdef CONFIG_VSX
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BEGIN_FTR_SECTION
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oris r3,r3,MSR_VSX@h
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END_FTR_SECTION_IFSET(CPU_FTR_VSX)
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#endif
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andc r4,r4,r3 /* disable FP for previous task */
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PPC_STL r4,_MSR-STACK_FRAME_OVERHEAD(r5)
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1:
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#ifndef CONFIG_SMP
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li r5,0
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LOAD_REG_ADDRBASE(r4,last_task_used_math)
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PPC_STL r5,ADDROFF(last_task_used_math)(r4)
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#endif /* CONFIG_SMP */
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blr
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/*
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* These are used in the alignment trap handler when emulating
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* single-precision loads and stores.
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*/
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_GLOBAL(cvt_fd)
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lfs 0,0(r3)
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stfd 0,0(r4)
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blr
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_GLOBAL(cvt_df)
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lfd 0,0(r3)
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stfs 0,0(r4)
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blr
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