mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-15 17:26:40 +07:00
dfcf5f3652
This adds a new chunk id to the CS ioctl to support the INDIRECT_BUFFER_CONST packet. On SI, the CP adds a new engine called the CE (Constant Engine) which runs simulatenously with the DE (Drawing Engine, formerly called the ME). This allows the CP to process two related IBs simultaneously. The CE is tasked with loading the constant data (constant buffers, resource descriptors, samplers, etc.) while the DE loads context register state and issues drawing commands. It's up to the userspace application to sychronize the CE and the DE using special synchronization packets. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Dave Airlie <airlied@redhat.com>
536 lines
15 KiB
C
536 lines
15 KiB
C
/*
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* Copyright 2008 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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* Copyright 2009 Jerome Glisse.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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* Jerome Glisse
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*/
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#include <linux/seq_file.h>
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#include <linux/slab.h>
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#include "drmP.h"
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#include "radeon_drm.h"
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#include "radeon_reg.h"
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#include "radeon.h"
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#include "atom.h"
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int radeon_debugfs_ib_init(struct radeon_device *rdev);
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int radeon_debugfs_ring_init(struct radeon_device *rdev);
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u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
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{
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struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
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u32 pg_idx, pg_offset;
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u32 idx_value = 0;
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int new_page;
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pg_idx = (idx * 4) / PAGE_SIZE;
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pg_offset = (idx * 4) % PAGE_SIZE;
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if (ibc->kpage_idx[0] == pg_idx)
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return ibc->kpage[0][pg_offset/4];
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if (ibc->kpage_idx[1] == pg_idx)
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return ibc->kpage[1][pg_offset/4];
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new_page = radeon_cs_update_pages(p, pg_idx);
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if (new_page < 0) {
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p->parser_error = new_page;
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return 0;
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}
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idx_value = ibc->kpage[new_page][pg_offset/4];
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return idx_value;
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}
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void radeon_ring_write(struct radeon_ring *ring, uint32_t v)
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{
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#if DRM_DEBUG_CODE
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if (ring->count_dw <= 0) {
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DRM_ERROR("radeon: writting more dword to ring than expected !\n");
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}
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#endif
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ring->ring[ring->wptr++] = v;
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ring->wptr &= ring->ptr_mask;
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ring->count_dw--;
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ring->ring_free_dw--;
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}
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/*
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* IB.
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*/
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bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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bool done = false;
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/* only free ib which have been emited */
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if (ib->fence && ib->fence->emitted) {
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if (radeon_fence_signaled(ib->fence)) {
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radeon_fence_unref(&ib->fence);
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radeon_sa_bo_free(rdev, &ib->sa_bo);
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done = true;
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}
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}
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return done;
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}
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int radeon_ib_get(struct radeon_device *rdev, int ring,
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struct radeon_ib **ib, unsigned size)
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{
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struct radeon_fence *fence;
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unsigned cretry = 0;
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int r = 0, i, idx;
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*ib = NULL;
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/* align size on 256 bytes */
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size = ALIGN(size, 256);
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r = radeon_fence_create(rdev, &fence, ring);
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if (r) {
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dev_err(rdev->dev, "failed to create fence for new IB\n");
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return r;
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}
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radeon_mutex_lock(&rdev->ib_pool.mutex);
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idx = rdev->ib_pool.head_id;
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retry:
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if (cretry > 5) {
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dev_err(rdev->dev, "failed to get an ib after 5 retry\n");
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radeon_mutex_unlock(&rdev->ib_pool.mutex);
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radeon_fence_unref(&fence);
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return -ENOMEM;
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}
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cretry++;
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for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
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radeon_ib_try_free(rdev, &rdev->ib_pool.ibs[idx]);
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if (rdev->ib_pool.ibs[idx].fence == NULL) {
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r = radeon_sa_bo_new(rdev, &rdev->ib_pool.sa_manager,
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&rdev->ib_pool.ibs[idx].sa_bo,
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size, 256);
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if (!r) {
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*ib = &rdev->ib_pool.ibs[idx];
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(*ib)->ptr = rdev->ib_pool.sa_manager.cpu_ptr;
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(*ib)->ptr += ((*ib)->sa_bo.offset >> 2);
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(*ib)->gpu_addr = rdev->ib_pool.sa_manager.gpu_addr;
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(*ib)->gpu_addr += (*ib)->sa_bo.offset;
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(*ib)->fence = fence;
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(*ib)->vm_id = 0;
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(*ib)->is_const_ib = false;
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/* ib are most likely to be allocated in a ring fashion
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* thus rdev->ib_pool.head_id should be the id of the
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* oldest ib
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*/
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rdev->ib_pool.head_id = (1 + idx);
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rdev->ib_pool.head_id &= (RADEON_IB_POOL_SIZE - 1);
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radeon_mutex_unlock(&rdev->ib_pool.mutex);
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return 0;
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}
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}
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idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
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}
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/* this should be rare event, ie all ib scheduled none signaled yet.
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*/
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for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
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if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) {
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r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false);
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if (!r) {
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goto retry;
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}
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/* an error happened */
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break;
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}
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idx = (idx + 1) & (RADEON_IB_POOL_SIZE - 1);
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}
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radeon_mutex_unlock(&rdev->ib_pool.mutex);
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radeon_fence_unref(&fence);
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return r;
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}
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void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
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{
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struct radeon_ib *tmp = *ib;
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*ib = NULL;
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if (tmp == NULL) {
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return;
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}
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radeon_mutex_lock(&rdev->ib_pool.mutex);
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if (tmp->fence && !tmp->fence->emitted) {
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radeon_sa_bo_free(rdev, &tmp->sa_bo);
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radeon_fence_unref(&tmp->fence);
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}
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radeon_mutex_unlock(&rdev->ib_pool.mutex);
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}
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int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib)
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{
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struct radeon_ring *ring = &rdev->ring[ib->fence->ring];
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int r = 0;
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if (!ib->length_dw || !ring->ready) {
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/* TODO: Nothings in the ib we should report. */
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DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx);
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return -EINVAL;
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}
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/* 64 dwords should be enough for fence too */
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r = radeon_ring_lock(rdev, ring, 64);
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if (r) {
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DRM_ERROR("radeon: scheduling IB failed (%d).\n", r);
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return r;
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}
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radeon_ring_ib_execute(rdev, ib->fence->ring, ib);
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radeon_fence_emit(rdev, ib->fence);
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radeon_ring_unlock_commit(rdev, ring);
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return 0;
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}
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int radeon_ib_pool_init(struct radeon_device *rdev)
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{
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struct radeon_sa_manager tmp;
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int i, r;
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r = radeon_sa_bo_manager_init(rdev, &tmp,
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RADEON_IB_POOL_SIZE*64*1024,
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RADEON_GEM_DOMAIN_GTT);
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if (r) {
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return r;
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}
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radeon_mutex_lock(&rdev->ib_pool.mutex);
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if (rdev->ib_pool.ready) {
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radeon_mutex_unlock(&rdev->ib_pool.mutex);
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radeon_sa_bo_manager_fini(rdev, &tmp);
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return 0;
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}
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rdev->ib_pool.sa_manager = tmp;
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INIT_LIST_HEAD(&rdev->ib_pool.sa_manager.sa_bo);
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for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
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rdev->ib_pool.ibs[i].fence = NULL;
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rdev->ib_pool.ibs[i].idx = i;
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rdev->ib_pool.ibs[i].length_dw = 0;
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INIT_LIST_HEAD(&rdev->ib_pool.ibs[i].sa_bo.list);
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}
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rdev->ib_pool.head_id = 0;
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rdev->ib_pool.ready = true;
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DRM_INFO("radeon: ib pool ready.\n");
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if (radeon_debugfs_ib_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for IB !\n");
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}
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if (radeon_debugfs_ring_init(rdev)) {
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DRM_ERROR("Failed to register debugfs file for rings !\n");
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}
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radeon_mutex_unlock(&rdev->ib_pool.mutex);
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return 0;
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}
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void radeon_ib_pool_fini(struct radeon_device *rdev)
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{
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unsigned i;
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radeon_mutex_lock(&rdev->ib_pool.mutex);
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if (rdev->ib_pool.ready) {
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for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
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radeon_sa_bo_free(rdev, &rdev->ib_pool.ibs[i].sa_bo);
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radeon_fence_unref(&rdev->ib_pool.ibs[i].fence);
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}
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radeon_sa_bo_manager_fini(rdev, &rdev->ib_pool.sa_manager);
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rdev->ib_pool.ready = false;
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}
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radeon_mutex_unlock(&rdev->ib_pool.mutex);
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}
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int radeon_ib_pool_start(struct radeon_device *rdev)
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{
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return radeon_sa_bo_manager_start(rdev, &rdev->ib_pool.sa_manager);
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}
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int radeon_ib_pool_suspend(struct radeon_device *rdev)
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{
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return radeon_sa_bo_manager_suspend(rdev, &rdev->ib_pool.sa_manager);
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}
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/*
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* Ring.
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*/
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int radeon_ring_index(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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/* r1xx-r5xx only has CP ring */
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if (rdev->family < CHIP_R600)
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return RADEON_RING_TYPE_GFX_INDEX;
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if (rdev->family >= CHIP_CAYMAN) {
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if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP1_INDEX])
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return CAYMAN_RING_TYPE_CP1_INDEX;
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else if (ring == &rdev->ring[CAYMAN_RING_TYPE_CP2_INDEX])
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return CAYMAN_RING_TYPE_CP2_INDEX;
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}
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return RADEON_RING_TYPE_GFX_INDEX;
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}
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void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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u32 rptr;
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if (rdev->wb.enabled)
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rptr = le32_to_cpu(rdev->wb.wb[ring->rptr_offs/4]);
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else
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rptr = RREG32(ring->rptr_reg);
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ring->rptr = (rptr & ring->ptr_reg_mask) >> ring->ptr_reg_shift;
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/* This works because ring_size is a power of 2 */
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ring->ring_free_dw = (ring->rptr + (ring->ring_size / 4));
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ring->ring_free_dw -= ring->wptr;
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ring->ring_free_dw &= ring->ptr_mask;
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if (!ring->ring_free_dw) {
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ring->ring_free_dw = ring->ring_size / 4;
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}
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}
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int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
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{
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int r;
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/* Align requested size with padding so unlock_commit can
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* pad safely */
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ndw = (ndw + ring->align_mask) & ~ring->align_mask;
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while (ndw > (ring->ring_free_dw - 1)) {
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radeon_ring_free_size(rdev, ring);
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if (ndw < ring->ring_free_dw) {
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break;
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}
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r = radeon_fence_wait_next(rdev, radeon_ring_index(rdev, ring));
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if (r)
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return r;
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}
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ring->count_dw = ndw;
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ring->wptr_old = ring->wptr;
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return 0;
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}
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int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ndw)
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{
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int r;
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mutex_lock(&ring->mutex);
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r = radeon_ring_alloc(rdev, ring, ndw);
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if (r) {
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mutex_unlock(&ring->mutex);
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return r;
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}
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return 0;
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}
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void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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unsigned count_dw_pad;
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unsigned i;
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/* We pad to match fetch size */
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count_dw_pad = (ring->align_mask + 1) -
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(ring->wptr & ring->align_mask);
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for (i = 0; i < count_dw_pad; i++) {
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radeon_ring_write(ring, ring->nop);
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}
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DRM_MEMORYBARRIER();
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WREG32(ring->wptr_reg, (ring->wptr << ring->ptr_reg_shift) & ring->ptr_reg_mask);
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(void)RREG32(ring->wptr_reg);
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}
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void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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radeon_ring_commit(rdev, ring);
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mutex_unlock(&ring->mutex);
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}
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void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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ring->wptr = ring->wptr_old;
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mutex_unlock(&ring->mutex);
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}
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int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *ring, unsigned ring_size,
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unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg,
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u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop)
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{
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int r;
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ring->ring_size = ring_size;
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ring->rptr_offs = rptr_offs;
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ring->rptr_reg = rptr_reg;
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ring->wptr_reg = wptr_reg;
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ring->ptr_reg_shift = ptr_reg_shift;
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ring->ptr_reg_mask = ptr_reg_mask;
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ring->nop = nop;
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/* Allocate ring buffer */
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if (ring->ring_obj == NULL) {
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r = radeon_bo_create(rdev, ring->ring_size, PAGE_SIZE, true,
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RADEON_GEM_DOMAIN_GTT,
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&ring->ring_obj);
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if (r) {
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dev_err(rdev->dev, "(%d) ring create failed\n", r);
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return r;
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}
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r = radeon_bo_reserve(ring->ring_obj, false);
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if (unlikely(r != 0))
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return r;
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r = radeon_bo_pin(ring->ring_obj, RADEON_GEM_DOMAIN_GTT,
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&ring->gpu_addr);
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if (r) {
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radeon_bo_unreserve(ring->ring_obj);
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dev_err(rdev->dev, "(%d) ring pin failed\n", r);
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return r;
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}
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r = radeon_bo_kmap(ring->ring_obj,
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(void **)&ring->ring);
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radeon_bo_unreserve(ring->ring_obj);
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if (r) {
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dev_err(rdev->dev, "(%d) ring map failed\n", r);
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return r;
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}
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}
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ring->ptr_mask = (ring->ring_size / 4) - 1;
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ring->ring_free_dw = ring->ring_size / 4;
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return 0;
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}
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void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *ring)
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{
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int r;
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struct radeon_bo *ring_obj;
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mutex_lock(&ring->mutex);
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ring_obj = ring->ring_obj;
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ring->ring = NULL;
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ring->ring_obj = NULL;
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mutex_unlock(&ring->mutex);
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if (ring_obj) {
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r = radeon_bo_reserve(ring_obj, false);
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if (likely(r == 0)) {
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radeon_bo_kunmap(ring_obj);
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radeon_bo_unpin(ring_obj);
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radeon_bo_unreserve(ring_obj);
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}
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radeon_bo_unref(&ring_obj);
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}
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}
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/*
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* Debugfs info
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*/
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#if defined(CONFIG_DEBUG_FS)
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static int radeon_debugfs_ring_info(struct seq_file *m, void *data)
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{
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struct drm_info_node *node = (struct drm_info_node *) m->private;
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struct drm_device *dev = node->minor->dev;
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struct radeon_device *rdev = dev->dev_private;
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int ridx = *(int*)node->info_ent->data;
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struct radeon_ring *ring = &rdev->ring[ridx];
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unsigned count, i, j;
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radeon_ring_free_size(rdev, ring);
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count = (ring->ring_size / 4) - ring->ring_free_dw;
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seq_printf(m, "wptr(0x%04x): 0x%08x\n", ring->wptr_reg, RREG32(ring->wptr_reg));
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seq_printf(m, "rptr(0x%04x): 0x%08x\n", ring->rptr_reg, RREG32(ring->rptr_reg));
|
|
seq_printf(m, "driver's copy of the wptr: 0x%08x\n", ring->wptr);
|
|
seq_printf(m, "driver's copy of the rptr: 0x%08x\n", ring->rptr);
|
|
seq_printf(m, "%u free dwords in ring\n", ring->ring_free_dw);
|
|
seq_printf(m, "%u dwords in ring\n", count);
|
|
i = ring->rptr;
|
|
for (j = 0; j <= count; j++) {
|
|
seq_printf(m, "r[%04d]=0x%08x\n", i, ring->ring[i]);
|
|
i = (i + 1) & ring->ptr_mask;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static int radeon_ring_type_gfx_index = RADEON_RING_TYPE_GFX_INDEX;
|
|
static int cayman_ring_type_cp1_index = CAYMAN_RING_TYPE_CP1_INDEX;
|
|
static int cayman_ring_type_cp2_index = CAYMAN_RING_TYPE_CP2_INDEX;
|
|
|
|
static struct drm_info_list radeon_debugfs_ring_info_list[] = {
|
|
{"radeon_ring_gfx", radeon_debugfs_ring_info, 0, &radeon_ring_type_gfx_index},
|
|
{"radeon_ring_cp1", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp1_index},
|
|
{"radeon_ring_cp2", radeon_debugfs_ring_info, 0, &cayman_ring_type_cp2_index},
|
|
};
|
|
|
|
static int radeon_debugfs_ib_info(struct seq_file *m, void *data)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
struct radeon_device *rdev = dev->dev_private;
|
|
struct radeon_ib *ib = &rdev->ib_pool.ibs[*((unsigned*)node->info_ent->data)];
|
|
unsigned i;
|
|
|
|
if (ib == NULL) {
|
|
return 0;
|
|
}
|
|
seq_printf(m, "IB %04u\n", ib->idx);
|
|
seq_printf(m, "IB fence %p\n", ib->fence);
|
|
seq_printf(m, "IB size %05u dwords\n", ib->length_dw);
|
|
for (i = 0; i < ib->length_dw; i++) {
|
|
seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE];
|
|
static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32];
|
|
static unsigned radeon_debugfs_ib_idx[RADEON_IB_POOL_SIZE];
|
|
#endif
|
|
|
|
int radeon_debugfs_ring_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
if (rdev->family >= CHIP_CAYMAN)
|
|
return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list,
|
|
ARRAY_SIZE(radeon_debugfs_ring_info_list));
|
|
else
|
|
return radeon_debugfs_add_files(rdev, radeon_debugfs_ring_info_list, 1);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|
|
|
|
int radeon_debugfs_ib_init(struct radeon_device *rdev)
|
|
{
|
|
#if defined(CONFIG_DEBUG_FS)
|
|
unsigned i;
|
|
|
|
for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
|
|
sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i);
|
|
radeon_debugfs_ib_idx[i] = i;
|
|
radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i];
|
|
radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info;
|
|
radeon_debugfs_ib_list[i].driver_features = 0;
|
|
radeon_debugfs_ib_list[i].data = &radeon_debugfs_ib_idx[i];
|
|
}
|
|
return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list,
|
|
RADEON_IB_POOL_SIZE);
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|