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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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6b7bfd8292
This patch moves PMU specific definitions into a new file as exynos-pmu.h. This will help in reducing dependency of common.h in pmu.c. Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com> Reviewed-by: Tomasz Figa <t.figa@samsung.com> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
179 lines
4.1 KiB
C
179 lines
4.1 KiB
C
/*
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* Copyright (c) 2011-2014 Samsung Electronics Co., Ltd.
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* http://www.samsung.com
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*
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* EXYNOS - Power Management support
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*
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* Based on arch/arm/mach-s3c2410/pm.c
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* Copyright (c) 2006 Simtec Electronics
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* Ben Dooks <ben@simtec.co.uk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/suspend.h>
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#include <linux/cpu_pm.h>
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#include <linux/io.h>
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#include <linux/err.h>
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#include <asm/firmware.h>
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#include <asm/smp_scu.h>
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#include <asm/suspend.h>
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#include <plat/pm-common.h>
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#include "common.h"
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#include "exynos-pmu.h"
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#include "regs-pmu.h"
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#include "regs-sys.h"
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static inline void __iomem *exynos_boot_vector_addr(void)
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{
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if (samsung_rev() == EXYNOS4210_REV_1_1)
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return pmu_base_addr + S5P_INFORM7;
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else if (samsung_rev() == EXYNOS4210_REV_1_0)
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return sysram_base_addr + 0x24;
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return pmu_base_addr + S5P_INFORM0;
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}
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static inline void __iomem *exynos_boot_vector_flag(void)
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{
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if (samsung_rev() == EXYNOS4210_REV_1_1)
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return pmu_base_addr + S5P_INFORM6;
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else if (samsung_rev() == EXYNOS4210_REV_1_0)
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return sysram_base_addr + 0x20;
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return pmu_base_addr + S5P_INFORM1;
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}
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#define S5P_CHECK_AFTR 0xFCBA0D10
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/* For Cortex-A9 Diagnostic and Power control register */
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static unsigned int save_arm_register[2];
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void exynos_cpu_save_register(void)
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{
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unsigned long tmp;
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/* Save Power control register */
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asm ("mrc p15, 0, %0, c15, c0, 0"
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: "=r" (tmp) : : "cc");
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save_arm_register[0] = tmp;
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/* Save Diagnostic register */
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asm ("mrc p15, 0, %0, c15, c0, 1"
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: "=r" (tmp) : : "cc");
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save_arm_register[1] = tmp;
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}
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void exynos_cpu_restore_register(void)
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{
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unsigned long tmp;
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/* Restore Power control register */
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tmp = save_arm_register[0];
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asm volatile ("mcr p15, 0, %0, c15, c0, 0"
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: : "r" (tmp)
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: "cc");
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/* Restore Diagnostic register */
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tmp = save_arm_register[1];
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asm volatile ("mcr p15, 0, %0, c15, c0, 1"
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: : "r" (tmp)
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: "cc");
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}
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void exynos_pm_central_suspend(void)
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{
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unsigned long tmp;
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/* Setting Central Sequence Register for power down mode */
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tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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tmp &= ~S5P_CENTRAL_LOWPWR_CFG;
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pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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/* Setting SEQ_OPTION register */
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pmu_raw_writel(S5P_USE_STANDBY_WFI0 | S5P_USE_STANDBY_WFE0,
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S5P_CENTRAL_SEQ_OPTION);
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}
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int exynos_pm_central_resume(void)
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{
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unsigned long tmp;
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/*
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* If PMU failed while entering sleep mode, WFI will be
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* ignored by PMU and then exiting cpu_do_idle().
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* S5P_CENTRAL_LOWPWR_CFG bit will not be set automatically
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* in this situation.
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*/
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tmp = pmu_raw_readl(S5P_CENTRAL_SEQ_CONFIGURATION);
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if (!(tmp & S5P_CENTRAL_LOWPWR_CFG)) {
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tmp |= S5P_CENTRAL_LOWPWR_CFG;
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pmu_raw_writel(tmp, S5P_CENTRAL_SEQ_CONFIGURATION);
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/* clear the wakeup state register */
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pmu_raw_writel(0x0, S5P_WAKEUP_STAT);
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/* No need to perform below restore code */
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return -1;
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}
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return 0;
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}
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/* Ext-GIC nIRQ/nFIQ is the only wakeup source in AFTR */
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static void exynos_set_wakeupmask(long mask)
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{
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pmu_raw_writel(mask, S5P_WAKEUP_MASK);
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}
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static void exynos_cpu_set_boot_vector(long flags)
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{
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__raw_writel(virt_to_phys(exynos_cpu_resume),
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exynos_boot_vector_addr());
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__raw_writel(flags, exynos_boot_vector_flag());
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}
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static int exynos_aftr_finisher(unsigned long flags)
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{
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int ret;
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exynos_set_wakeupmask(0x0000ff3e);
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/* Set value of power down register for aftr mode */
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exynos_sys_powerdown_conf(SYS_AFTR);
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ret = call_firmware_op(do_idle, FW_DO_IDLE_AFTR);
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if (ret == -ENOSYS) {
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9)
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exynos_cpu_save_register();
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exynos_cpu_set_boot_vector(S5P_CHECK_AFTR);
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cpu_do_idle();
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}
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return 1;
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}
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void exynos_enter_aftr(void)
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{
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cpu_pm_enter();
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exynos_pm_central_suspend();
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cpu_suspend(0, exynos_aftr_finisher);
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if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) {
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scu_enable(S5P_VA_SCU);
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if (call_firmware_op(resume) == -ENOSYS)
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exynos_cpu_restore_register();
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}
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exynos_pm_central_resume();
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cpu_pm_exit();
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}
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