mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-24 22:57:27 +07:00
6b57ba8ed4
There are many different formats in each header now, such as _ASM_XXX_H, __ASM_XXX_H, _ASM_RISCV_XXX_H, RISCV_XXX_H, etc., This patch tries to unify the format by using _ASM_RISCV_XXX_H, because the most header use it now. This patch also adds the conditional to the headers if they lost it. Signed-off-by: Zong Li <zong.li@sifive.com> Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
28 lines
509 B
C
28 lines
509 B
C
/* SPDX-License-Identifier: GPL-2.0-only */
|
|
/*
|
|
* Copied from arch/arm64/include/asm/hwcap.h
|
|
*
|
|
* Copyright (C) 2012 ARM Ltd.
|
|
* Copyright (C) 2017 SiFive
|
|
*/
|
|
#ifndef _ASM_RISCV_HWCAP_H
|
|
#define _ASM_RISCV_HWCAP_H
|
|
|
|
#include <uapi/asm/hwcap.h>
|
|
|
|
#ifndef __ASSEMBLY__
|
|
/*
|
|
* This yields a mask that user programs can use to figure out what
|
|
* instruction set this cpu supports.
|
|
*/
|
|
#define ELF_HWCAP (elf_hwcap)
|
|
|
|
enum {
|
|
CAP_HWCAP = 1,
|
|
};
|
|
|
|
extern unsigned long elf_hwcap;
|
|
#endif
|
|
|
|
#endif /* _ASM_RISCV_HWCAP_H */
|