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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c68a903229
When the kernel is running in S-mode, the expectation is that the bootloader or SBI layer will configure the PMP to allow the kernel to access physical memory. But, when the kernel is running in M-mode and is started with the ELF "loader", there's probably no bootloader or SBI layer involved to configure the PMP. Thus, we need to configure the PMP ourselves to enable the kernel to access all regions. Signed-off-by: Greentime Hu <greentime.hu@sifive.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
223 lines
5.7 KiB
C
223 lines
5.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2015 Regents of the University of California
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*/
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#ifndef _ASM_RISCV_CSR_H
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#define _ASM_RISCV_CSR_H
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#include <asm/asm.h>
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#include <linux/const.h>
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/* Status register flags */
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#define SR_SIE _AC(0x00000002, UL) /* Supervisor Interrupt Enable */
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#define SR_MIE _AC(0x00000008, UL) /* Machine Interrupt Enable */
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#define SR_SPIE _AC(0x00000020, UL) /* Previous Supervisor IE */
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#define SR_MPIE _AC(0x00000080, UL) /* Previous Machine IE */
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#define SR_SPP _AC(0x00000100, UL) /* Previously Supervisor */
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#define SR_MPP _AC(0x00001800, UL) /* Previously Machine */
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#define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */
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#define SR_FS _AC(0x00006000, UL) /* Floating-point Status */
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#define SR_FS_OFF _AC(0x00000000, UL)
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#define SR_FS_INITIAL _AC(0x00002000, UL)
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#define SR_FS_CLEAN _AC(0x00004000, UL)
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#define SR_FS_DIRTY _AC(0x00006000, UL)
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#define SR_XS _AC(0x00018000, UL) /* Extension Status */
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#define SR_XS_OFF _AC(0x00000000, UL)
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#define SR_XS_INITIAL _AC(0x00008000, UL)
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#define SR_XS_CLEAN _AC(0x00010000, UL)
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#define SR_XS_DIRTY _AC(0x00018000, UL)
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#ifndef CONFIG_64BIT
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#define SR_SD _AC(0x80000000, UL) /* FS/XS dirty */
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#else
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#define SR_SD _AC(0x8000000000000000, UL) /* FS/XS dirty */
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#endif
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/* SATP flags */
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#ifndef CONFIG_64BIT
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#define SATP_PPN _AC(0x003FFFFF, UL)
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#define SATP_MODE_32 _AC(0x80000000, UL)
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#define SATP_MODE SATP_MODE_32
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#else
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#define SATP_PPN _AC(0x00000FFFFFFFFFFF, UL)
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#define SATP_MODE_39 _AC(0x8000000000000000, UL)
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#define SATP_MODE SATP_MODE_39
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#endif
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/* Exception cause high bit - is an interrupt if set */
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#define CAUSE_IRQ_FLAG (_AC(1, UL) << (__riscv_xlen - 1))
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/* Interrupt causes (minus the high bit) */
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#define IRQ_U_SOFT 0
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#define IRQ_S_SOFT 1
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#define IRQ_M_SOFT 3
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#define IRQ_U_TIMER 4
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#define IRQ_S_TIMER 5
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#define IRQ_M_TIMER 7
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#define IRQ_U_EXT 8
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#define IRQ_S_EXT 9
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#define IRQ_M_EXT 11
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/* Exception causes */
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#define EXC_INST_MISALIGNED 0
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#define EXC_INST_ACCESS 1
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#define EXC_BREAKPOINT 3
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#define EXC_LOAD_ACCESS 5
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#define EXC_STORE_ACCESS 7
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#define EXC_SYSCALL 8
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#define EXC_INST_PAGE_FAULT 12
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#define EXC_LOAD_PAGE_FAULT 13
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#define EXC_STORE_PAGE_FAULT 15
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/* PMP configuration */
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#define PMP_R 0x01
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#define PMP_W 0x02
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#define PMP_X 0x04
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#define PMP_A 0x18
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#define PMP_A_TOR 0x08
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#define PMP_A_NA4 0x10
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#define PMP_A_NAPOT 0x18
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#define PMP_L 0x80
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/* symbolic CSR names: */
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#define CSR_CYCLE 0xc00
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#define CSR_TIME 0xc01
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#define CSR_INSTRET 0xc02
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#define CSR_CYCLEH 0xc80
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#define CSR_TIMEH 0xc81
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#define CSR_INSTRETH 0xc82
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#define CSR_SSTATUS 0x100
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#define CSR_SIE 0x104
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#define CSR_STVEC 0x105
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#define CSR_SCOUNTEREN 0x106
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#define CSR_SSCRATCH 0x140
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#define CSR_SEPC 0x141
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#define CSR_SCAUSE 0x142
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#define CSR_STVAL 0x143
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#define CSR_SIP 0x144
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#define CSR_SATP 0x180
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#define CSR_MSTATUS 0x300
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#define CSR_MISA 0x301
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#define CSR_MIE 0x304
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#define CSR_MTVEC 0x305
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#define CSR_MSCRATCH 0x340
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#define CSR_MEPC 0x341
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#define CSR_MCAUSE 0x342
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#define CSR_MTVAL 0x343
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#define CSR_MIP 0x344
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#define CSR_PMPCFG0 0x3a0
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#define CSR_PMPADDR0 0x3b0
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#define CSR_MHARTID 0xf14
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#ifdef CONFIG_RISCV_M_MODE
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# define CSR_STATUS CSR_MSTATUS
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# define CSR_IE CSR_MIE
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# define CSR_TVEC CSR_MTVEC
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# define CSR_SCRATCH CSR_MSCRATCH
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# define CSR_EPC CSR_MEPC
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# define CSR_CAUSE CSR_MCAUSE
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# define CSR_TVAL CSR_MTVAL
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# define CSR_IP CSR_MIP
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# define SR_IE SR_MIE
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# define SR_PIE SR_MPIE
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# define SR_PP SR_MPP
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# define RV_IRQ_SOFT IRQ_M_SOFT
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# define RV_IRQ_TIMER IRQ_M_TIMER
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# define RV_IRQ_EXT IRQ_M_EXT
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#else /* CONFIG_RISCV_M_MODE */
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# define CSR_STATUS CSR_SSTATUS
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# define CSR_IE CSR_SIE
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# define CSR_TVEC CSR_STVEC
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# define CSR_SCRATCH CSR_SSCRATCH
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# define CSR_EPC CSR_SEPC
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# define CSR_CAUSE CSR_SCAUSE
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# define CSR_TVAL CSR_STVAL
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# define CSR_IP CSR_SIP
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# define SR_IE SR_SIE
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# define SR_PIE SR_SPIE
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# define SR_PP SR_SPP
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# define RV_IRQ_SOFT IRQ_S_SOFT
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# define RV_IRQ_TIMER IRQ_S_TIMER
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# define RV_IRQ_EXT IRQ_S_EXT
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#endif /* CONFIG_RISCV_M_MODE */
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/* IE/IP (Supervisor/Machine Interrupt Enable/Pending) flags */
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#define IE_SIE (_AC(0x1, UL) << RV_IRQ_SOFT)
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#define IE_TIE (_AC(0x1, UL) << RV_IRQ_TIMER)
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#define IE_EIE (_AC(0x1, UL) << RV_IRQ_EXT)
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#ifndef __ASSEMBLY__
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#define csr_swap(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrw %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_read(csr) \
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({ \
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register unsigned long __v; \
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__asm__ __volatile__ ("csrr %0, " __ASM_STR(csr) \
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: "=r" (__v) : \
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: "memory"); \
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__v; \
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})
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#define csr_write(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrw " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrs %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_set(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrs " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#define csr_read_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrrc %0, " __ASM_STR(csr) ", %1"\
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: "=r" (__v) : "rK" (__v) \
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: "memory"); \
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__v; \
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})
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#define csr_clear(csr, val) \
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({ \
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unsigned long __v = (unsigned long)(val); \
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__asm__ __volatile__ ("csrc " __ASM_STR(csr) ", %0" \
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: : "rK" (__v) \
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: "memory"); \
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})
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_RISCV_CSR_H */
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