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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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990f2f223c
The mmp clock drivers currently hardcode the physical addresses for the clock registers. This is generally a bad idea, and it also gets in the way of multiplatform builds, which make the platform header files inaccessible to device drivers. To work around the header file problem, this patch changes the calling convention so the three mmp clock drivers get initialized with the base addresses as arguments from the platform code. It would still be useful to have a larger rework of the clock drivers, with DT integration to let the clocks actually be probed automatically, and the base addresses passed as DT properties. I am unsure if anyone is still interested in the mmp platform, so it is possible that this won't happen. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Mike Turquette <mturquette@linaro.org> Cc: Chao Xie <chao.xie@marvell.com> Cc: Eric Miao <eric.y.miao@gmail.com> Cc: Haojian Zhuang <haojian.zhuang@gmail.com>
461 lines
15 KiB
C
461 lines
15 KiB
C
/*
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* mmp2 clock framework source file
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*
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* Copyright (C) 2012 Marvell
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* Chao Xie <xiechao.mail@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/clk.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include "clk.h"
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#define APBC_RTC 0x0
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#define APBC_TWSI0 0x4
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#define APBC_TWSI1 0x8
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#define APBC_TWSI2 0xc
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#define APBC_TWSI3 0x10
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#define APBC_TWSI4 0x7c
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#define APBC_TWSI5 0x80
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#define APBC_KPC 0x18
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#define APBC_UART0 0x2c
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#define APBC_UART1 0x30
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#define APBC_UART2 0x34
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#define APBC_UART3 0x88
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#define APBC_GPIO 0x38
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#define APBC_PWM0 0x3c
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#define APBC_PWM1 0x40
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#define APBC_PWM2 0x44
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#define APBC_PWM3 0x48
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#define APBC_SSP0 0x50
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#define APBC_SSP1 0x54
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#define APBC_SSP2 0x58
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#define APBC_SSP3 0x5c
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#define APMU_SDH0 0x54
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#define APMU_SDH1 0x58
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#define APMU_SDH2 0xe8
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#define APMU_SDH3 0xec
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#define APMU_USB 0x5c
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#define APMU_DISP0 0x4c
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#define APMU_DISP1 0x110
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#define APMU_CCIC0 0x50
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#define APMU_CCIC1 0xf4
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#define MPMU_UART_PLL 0x14
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static DEFINE_SPINLOCK(clk_lock);
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static struct mmp_clk_factor_masks uart_factor_masks = {
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.factor = 2,
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.num_mask = 0x1fff,
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.den_mask = 0x1fff,
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.num_shift = 16,
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.den_shift = 0,
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};
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static struct mmp_clk_factor_tbl uart_factor_tbl[] = {
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{.num = 8125, .den = 1536}, /*14.745MHZ */
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{.num = 3521, .den = 689}, /*19.23MHZ */
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};
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static const char *uart_parent[] = {"uart_pll", "vctcxo"};
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static const char *ssp_parent[] = {"vctcxo_4", "vctcxo_2", "vctcxo", "pll1_16"};
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static const char *sdh_parent[] = {"pll1_4", "pll2", "usb_pll", "pll1"};
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static const char *disp_parent[] = {"pll1", "pll1_16", "pll2", "vctcxo"};
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static const char *ccic_parent[] = {"pll1_2", "pll1_16", "vctcxo"};
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void __init mmp2_clk_init(phys_addr_t mpmu_phys, phys_addr_t apmu_phys,
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phys_addr_t apbc_phys)
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{
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struct clk *clk;
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struct clk *vctcxo;
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void __iomem *mpmu_base;
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void __iomem *apmu_base;
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void __iomem *apbc_base;
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mpmu_base = ioremap(mpmu_phys, SZ_4K);
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if (mpmu_base == NULL) {
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pr_err("error to ioremap MPMU base\n");
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return;
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}
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apmu_base = ioremap(apmu_phys, SZ_4K);
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if (apmu_base == NULL) {
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pr_err("error to ioremap APMU base\n");
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return;
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}
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apbc_base = ioremap(apbc_phys, SZ_4K);
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if (apbc_base == NULL) {
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pr_err("error to ioremap APBC base\n");
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return;
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}
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clk = clk_register_fixed_rate(NULL, "clk32", NULL, CLK_IS_ROOT, 3200);
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clk_register_clkdev(clk, "clk32", NULL);
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vctcxo = clk_register_fixed_rate(NULL, "vctcxo", NULL, CLK_IS_ROOT,
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26000000);
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clk_register_clkdev(vctcxo, "vctcxo", NULL);
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clk = clk_register_fixed_rate(NULL, "pll1", NULL, CLK_IS_ROOT,
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800000000);
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clk_register_clkdev(clk, "pll1", NULL);
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clk = clk_register_fixed_rate(NULL, "usb_pll", NULL, CLK_IS_ROOT,
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480000000);
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clk_register_clkdev(clk, "usb_pll", NULL);
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clk = clk_register_fixed_rate(NULL, "pll2", NULL, CLK_IS_ROOT,
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960000000);
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clk_register_clkdev(clk, "pll2", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_2", "pll1",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_2", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_4", "pll1_2",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_4", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_8", "pll1_4",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_8", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_16", "pll1_8",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_16", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_20", "pll1_4",
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CLK_SET_RATE_PARENT, 1, 5);
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clk_register_clkdev(clk, "pll1_20", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_3", "pll1",
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CLK_SET_RATE_PARENT, 1, 3);
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clk_register_clkdev(clk, "pll1_3", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_6", "pll1_3",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_6", NULL);
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clk = clk_register_fixed_factor(NULL, "pll1_12", "pll1_6",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll1_12", NULL);
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clk = clk_register_fixed_factor(NULL, "pll2_2", "pll2",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll2_2", NULL);
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clk = clk_register_fixed_factor(NULL, "pll2_4", "pll2_2",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll2_4", NULL);
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clk = clk_register_fixed_factor(NULL, "pll2_8", "pll2_4",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll2_8", NULL);
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clk = clk_register_fixed_factor(NULL, "pll2_16", "pll2_8",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll2_16", NULL);
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clk = clk_register_fixed_factor(NULL, "pll2_3", "pll2",
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CLK_SET_RATE_PARENT, 1, 3);
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clk_register_clkdev(clk, "pll2_3", NULL);
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clk = clk_register_fixed_factor(NULL, "pll2_6", "pll2_3",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll2_6", NULL);
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clk = clk_register_fixed_factor(NULL, "pll2_12", "pll2_6",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "pll2_12", NULL);
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clk = clk_register_fixed_factor(NULL, "vctcxo_2", "vctcxo",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "vctcxo_2", NULL);
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clk = clk_register_fixed_factor(NULL, "vctcxo_4", "vctcxo_2",
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CLK_SET_RATE_PARENT, 1, 2);
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clk_register_clkdev(clk, "vctcxo_4", NULL);
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clk = mmp_clk_register_factor("uart_pll", "pll1_4", 0,
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mpmu_base + MPMU_UART_PLL,
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&uart_factor_masks, uart_factor_tbl,
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ARRAY_SIZE(uart_factor_tbl), &clk_lock);
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clk_set_rate(clk, 14745600);
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clk_register_clkdev(clk, "uart_pll", NULL);
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clk = mmp_clk_register_apbc("twsi0", "vctcxo",
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apbc_base + APBC_TWSI0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.0");
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clk = mmp_clk_register_apbc("twsi1", "vctcxo",
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apbc_base + APBC_TWSI1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.1");
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clk = mmp_clk_register_apbc("twsi2", "vctcxo",
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apbc_base + APBC_TWSI2, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.2");
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clk = mmp_clk_register_apbc("twsi3", "vctcxo",
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apbc_base + APBC_TWSI3, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.3");
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clk = mmp_clk_register_apbc("twsi4", "vctcxo",
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apbc_base + APBC_TWSI4, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.4");
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clk = mmp_clk_register_apbc("twsi5", "vctcxo",
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apbc_base + APBC_TWSI5, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-i2c.5");
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clk = mmp_clk_register_apbc("gpio", "vctcxo",
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apbc_base + APBC_GPIO, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp2-gpio");
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clk = mmp_clk_register_apbc("kpc", "clk32",
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apbc_base + APBC_KPC, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa27x-keypad");
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clk = mmp_clk_register_apbc("rtc", "clk32",
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apbc_base + APBC_RTC, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-rtc");
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clk = mmp_clk_register_apbc("pwm0", "vctcxo",
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apbc_base + APBC_PWM0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp2-pwm.0");
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clk = mmp_clk_register_apbc("pwm1", "vctcxo",
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apbc_base + APBC_PWM1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp2-pwm.1");
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clk = mmp_clk_register_apbc("pwm2", "vctcxo",
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apbc_base + APBC_PWM2, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp2-pwm.2");
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clk = mmp_clk_register_apbc("pwm3", "vctcxo",
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apbc_base + APBC_PWM3, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp2-pwm.3");
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clk = clk_register_mux(NULL, "uart0_mux", uart_parent,
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ARRAY_SIZE(uart_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_UART0, 4, 3, 0, &clk_lock);
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clk_set_parent(clk, vctcxo);
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clk_register_clkdev(clk, "uart_mux.0", NULL);
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clk = mmp_clk_register_apbc("uart0", "uart0_mux",
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apbc_base + APBC_UART0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-uart.0");
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clk = clk_register_mux(NULL, "uart1_mux", uart_parent,
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ARRAY_SIZE(uart_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_UART1, 4, 3, 0, &clk_lock);
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clk_set_parent(clk, vctcxo);
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clk_register_clkdev(clk, "uart_mux.1", NULL);
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clk = mmp_clk_register_apbc("uart1", "uart1_mux",
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apbc_base + APBC_UART1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-uart.1");
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clk = clk_register_mux(NULL, "uart2_mux", uart_parent,
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ARRAY_SIZE(uart_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_UART2, 4, 3, 0, &clk_lock);
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clk_set_parent(clk, vctcxo);
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clk_register_clkdev(clk, "uart_mux.2", NULL);
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clk = mmp_clk_register_apbc("uart2", "uart2_mux",
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apbc_base + APBC_UART2, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-uart.2");
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clk = clk_register_mux(NULL, "uart3_mux", uart_parent,
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ARRAY_SIZE(uart_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_UART3, 4, 3, 0, &clk_lock);
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clk_set_parent(clk, vctcxo);
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clk_register_clkdev(clk, "uart_mux.3", NULL);
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clk = mmp_clk_register_apbc("uart3", "uart3_mux",
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apbc_base + APBC_UART3, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "pxa2xx-uart.3");
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clk = clk_register_mux(NULL, "ssp0_mux", ssp_parent,
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ARRAY_SIZE(ssp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_SSP0, 4, 3, 0, &clk_lock);
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clk_register_clkdev(clk, "uart_mux.0", NULL);
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clk = mmp_clk_register_apbc("ssp0", "ssp0_mux",
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apbc_base + APBC_SSP0, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-ssp.0");
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clk = clk_register_mux(NULL, "ssp1_mux", ssp_parent,
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ARRAY_SIZE(ssp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_SSP1, 4, 3, 0, &clk_lock);
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clk_register_clkdev(clk, "ssp_mux.1", NULL);
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clk = mmp_clk_register_apbc("ssp1", "ssp1_mux",
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apbc_base + APBC_SSP1, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-ssp.1");
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clk = clk_register_mux(NULL, "ssp2_mux", ssp_parent,
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ARRAY_SIZE(ssp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_SSP2, 4, 3, 0, &clk_lock);
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clk_register_clkdev(clk, "ssp_mux.2", NULL);
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clk = mmp_clk_register_apbc("ssp2", "ssp2_mux",
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apbc_base + APBC_SSP2, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-ssp.2");
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clk = clk_register_mux(NULL, "ssp3_mux", ssp_parent,
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ARRAY_SIZE(ssp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apbc_base + APBC_SSP3, 4, 3, 0, &clk_lock);
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clk_register_clkdev(clk, "ssp_mux.3", NULL);
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clk = mmp_clk_register_apbc("ssp3", "ssp3_mux",
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apbc_base + APBC_SSP3, 10, 0, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-ssp.3");
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clk = clk_register_mux(NULL, "sdh_mux", sdh_parent,
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ARRAY_SIZE(sdh_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apmu_base + APMU_SDH0, 8, 2, 0, &clk_lock);
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clk_register_clkdev(clk, "sdh_mux", NULL);
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clk = clk_register_divider(NULL, "sdh_div", "sdh_mux",
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CLK_SET_RATE_PARENT, apmu_base + APMU_SDH0,
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10, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
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clk_register_clkdev(clk, "sdh_div", NULL);
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clk = mmp_clk_register_apmu("sdh0", "sdh_div", apmu_base + APMU_SDH0,
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0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "sdhci-pxav3.0");
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clk = mmp_clk_register_apmu("sdh1", "sdh_div", apmu_base + APMU_SDH1,
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0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "sdhci-pxav3.1");
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clk = mmp_clk_register_apmu("sdh2", "sdh_div", apmu_base + APMU_SDH2,
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0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "sdhci-pxav3.2");
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clk = mmp_clk_register_apmu("sdh3", "sdh_div", apmu_base + APMU_SDH3,
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0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "sdhci-pxav3.3");
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clk = mmp_clk_register_apmu("usb", "usb_pll", apmu_base + APMU_USB,
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0x9, &clk_lock);
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clk_register_clkdev(clk, "usb_clk", NULL);
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clk = clk_register_mux(NULL, "disp0_mux", disp_parent,
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ARRAY_SIZE(disp_parent),
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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apmu_base + APMU_DISP0, 6, 2, 0, &clk_lock);
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clk_register_clkdev(clk, "disp_mux.0", NULL);
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clk = clk_register_divider(NULL, "disp0_div", "disp0_mux",
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CLK_SET_RATE_PARENT, apmu_base + APMU_DISP0,
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8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
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clk_register_clkdev(clk, "disp_div.0", NULL);
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clk = mmp_clk_register_apmu("disp0", "disp0_div",
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apmu_base + APMU_DISP0, 0x1b, &clk_lock);
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clk_register_clkdev(clk, NULL, "mmp-disp.0");
|
|
|
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clk = clk_register_divider(NULL, "disp0_sphy_div", "disp0_mux", 0,
|
|
apmu_base + APMU_DISP0, 15, 5, 0, &clk_lock);
|
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clk_register_clkdev(clk, "disp_sphy_div.0", NULL);
|
|
|
|
clk = mmp_clk_register_apmu("disp0_sphy", "disp0_sphy_div",
|
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apmu_base + APMU_DISP0, 0x1024, &clk_lock);
|
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clk_register_clkdev(clk, "disp_sphy.0", NULL);
|
|
|
|
clk = clk_register_mux(NULL, "disp1_mux", disp_parent,
|
|
ARRAY_SIZE(disp_parent),
|
|
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
|
apmu_base + APMU_DISP1, 6, 2, 0, &clk_lock);
|
|
clk_register_clkdev(clk, "disp_mux.1", NULL);
|
|
|
|
clk = clk_register_divider(NULL, "disp1_div", "disp1_mux",
|
|
CLK_SET_RATE_PARENT, apmu_base + APMU_DISP1,
|
|
8, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
|
clk_register_clkdev(clk, "disp_div.1", NULL);
|
|
|
|
clk = mmp_clk_register_apmu("disp1", "disp1_div",
|
|
apmu_base + APMU_DISP1, 0x1b, &clk_lock);
|
|
clk_register_clkdev(clk, NULL, "mmp-disp.1");
|
|
|
|
clk = mmp_clk_register_apmu("ccic_arbiter", "vctcxo",
|
|
apmu_base + APMU_CCIC0, 0x1800, &clk_lock);
|
|
clk_register_clkdev(clk, "ccic_arbiter", NULL);
|
|
|
|
clk = clk_register_mux(NULL, "ccic0_mux", ccic_parent,
|
|
ARRAY_SIZE(ccic_parent),
|
|
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
|
apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock);
|
|
clk_register_clkdev(clk, "ccic_mux.0", NULL);
|
|
|
|
clk = clk_register_divider(NULL, "ccic0_div", "ccic0_mux",
|
|
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
|
|
17, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
|
clk_register_clkdev(clk, "ccic_div.0", NULL);
|
|
|
|
clk = mmp_clk_register_apmu("ccic0", "ccic0_div",
|
|
apmu_base + APMU_CCIC0, 0x1b, &clk_lock);
|
|
clk_register_clkdev(clk, "fnclk", "mmp-ccic.0");
|
|
|
|
clk = mmp_clk_register_apmu("ccic0_phy", "ccic0_div",
|
|
apmu_base + APMU_CCIC0, 0x24, &clk_lock);
|
|
clk_register_clkdev(clk, "phyclk", "mmp-ccic.0");
|
|
|
|
clk = clk_register_divider(NULL, "ccic0_sphy_div", "ccic0_div",
|
|
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0,
|
|
10, 5, 0, &clk_lock);
|
|
clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.0");
|
|
|
|
clk = mmp_clk_register_apmu("ccic0_sphy", "ccic0_sphy_div",
|
|
apmu_base + APMU_CCIC0, 0x300, &clk_lock);
|
|
clk_register_clkdev(clk, "sphyclk", "mmp-ccic.0");
|
|
|
|
clk = clk_register_mux(NULL, "ccic1_mux", ccic_parent,
|
|
ARRAY_SIZE(ccic_parent),
|
|
CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
|
|
apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock);
|
|
clk_register_clkdev(clk, "ccic_mux.1", NULL);
|
|
|
|
clk = clk_register_divider(NULL, "ccic1_div", "ccic1_mux",
|
|
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
|
|
16, 4, CLK_DIVIDER_ONE_BASED, &clk_lock);
|
|
clk_register_clkdev(clk, "ccic_div.1", NULL);
|
|
|
|
clk = mmp_clk_register_apmu("ccic1", "ccic1_div",
|
|
apmu_base + APMU_CCIC1, 0x1b, &clk_lock);
|
|
clk_register_clkdev(clk, "fnclk", "mmp-ccic.1");
|
|
|
|
clk = mmp_clk_register_apmu("ccic1_phy", "ccic1_div",
|
|
apmu_base + APMU_CCIC1, 0x24, &clk_lock);
|
|
clk_register_clkdev(clk, "phyclk", "mmp-ccic.1");
|
|
|
|
clk = clk_register_divider(NULL, "ccic1_sphy_div", "ccic1_div",
|
|
CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1,
|
|
10, 5, 0, &clk_lock);
|
|
clk_register_clkdev(clk, "sphyclk_div", "mmp-ccic.1");
|
|
|
|
clk = mmp_clk_register_apmu("ccic1_sphy", "ccic1_sphy_div",
|
|
apmu_base + APMU_CCIC1, 0x300, &clk_lock);
|
|
clk_register_clkdev(clk, "sphyclk", "mmp-ccic.1");
|
|
}
|