mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-19 11:48:43 +07:00
070e386727
commit 11a163f2c7d6a9f27ce144cd7e367a81c851621a upstream.
The previous code assumed that a higher hardware value always resulted
in a bigger divider, which is correct for the regular clocks, but is
an invalid assumption when a divider table is provided for the clock.
Perfect example of this is the PLL0_HALF clock, which applies a /2
divider with the hardware value 0, and a /1 divider otherwise.
Fixes:
|
||
|---|---|---|
| .. | ||
| cgu.c | ||
| cgu.h | ||
| jz4725b-cgu.c | ||
| jz4740-cgu.c | ||
| jz4770-cgu.c | ||
| jz4780-cgu.c | ||
| Kconfig | ||
| Makefile | ||
| pm.c | ||
| pm.h | ||
| tcu.c | ||
| x1000-cgu.c | ||
| x1830-cgu.c | ||