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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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bc2eca9a68
The ldrd and strd instructions work on a pair of consecutive registers. It is possible to specify either the first register in the pair, or both registers explicitly. Let's always do the later to make things clearer. Signed-off-by: Nicolas Pitre <nico@linaro.org> Suggested-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
89 lines
2.0 KiB
ArmAsm
89 lines
2.0 KiB
ArmAsm
/*
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* Copyright (C) 2015 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This assembly is required to safely remap the physical address space
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* for Keystone 2
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/cp15.h>
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#include <asm/memory.h>
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#include <asm/pgtable.h>
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.section ".idmap.text", "ax"
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#define L1_ORDER 3
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#define L2_ORDER 3
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ENTRY(lpae_pgtables_remap_asm)
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stmfd sp!, {r4-r8, lr}
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mrc p15, 0, r8, c1, c0, 0 @ read control reg
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bic ip, r8, #CR_M @ disable caches and MMU
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mcr p15, 0, ip, c1, c0, 0
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dsb
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isb
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/* Update level 2 entries covering the kernel */
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ldr r6, =(_end - 1)
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add r7, r2, #0x1000
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add r6, r7, r6, lsr #SECTION_SHIFT - L2_ORDER
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add r7, r7, #PAGE_OFFSET >> (SECTION_SHIFT - L2_ORDER)
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1: ldrd r4, r5, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, r5, [r7], #1 << L2_ORDER
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cmp r7, r6
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bls 1b
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/* Update level 2 entries for the boot data */
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add r7, r2, #0x1000
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add r7, r7, r3, lsr #SECTION_SHIFT - L2_ORDER
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bic r7, r7, #(1 << L2_ORDER) - 1
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ldrd r4, r5, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, r5, [r7], #1 << L2_ORDER
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ldrd r4, r5, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, r5, [r7]
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/* Update level 1 entries */
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mov r6, #4
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mov r7, r2
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2: ldrd r4, r5, [r7]
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adds r4, r4, r0
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adc r5, r5, r1
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strd r4, r5, [r7], #1 << L1_ORDER
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subs r6, r6, #1
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bne 2b
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mrrc p15, 0, r4, r5, c2 @ read TTBR0
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adds r4, r4, r0 @ update physical address
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adc r5, r5, r1
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mcrr p15, 0, r4, r5, c2 @ write back TTBR0
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mrrc p15, 1, r4, r5, c2 @ read TTBR1
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adds r4, r4, r0 @ update physical address
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adc r5, r5, r1
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mcrr p15, 1, r4, r5, c2 @ write back TTBR1
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dsb
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mov ip, #0
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mcr p15, 0, ip, c7, c5, 0 @ I+BTB cache invalidate
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mcr p15, 0, ip, c8, c7, 0 @ local_flush_tlb_all()
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dsb
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isb
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mcr p15, 0, r8, c1, c0, 0 @ re-enable MMU
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dsb
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isb
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ldmfd sp!, {r4-r8, pc}
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ENDPROC(lpae_pgtables_remap_asm)
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