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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not see http www gnu org licenses extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 503 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Enrico Weigelt <info@metux.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190602204653.811534538@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
122 lines
2.6 KiB
ArmAsm
122 lines
2.6 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (C) 2016 - ARM Ltd
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* Author: Marc Zyngier <marc.zyngier@arm.com>
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*/
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#include <linux/linkage.h>
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#include <asm/asm-offsets.h>
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#include <asm/kvm_arm.h>
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#include <asm/kvm_asm.h>
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.arch_extension virt
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.text
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.pushsection .hyp.text, "ax"
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#define USR_REGS_OFFSET (CPU_CTXT_GP_REGS + GP_REGS_USR)
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/* int __guest_enter(struct kvm_vcpu *vcpu, struct kvm_cpu_context *host) */
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ENTRY(__guest_enter)
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@ Save host registers
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add r1, r1, #(USR_REGS_OFFSET + S_R4)
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stm r1!, {r4-r12}
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str lr, [r1, #4] @ Skip SP_usr (already saved)
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@ Restore guest registers
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add r0, r0, #(VCPU_GUEST_CTXT + USR_REGS_OFFSET + S_R0)
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ldr lr, [r0, #S_LR]
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ldm r0, {r0-r12}
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clrex
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eret
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ENDPROC(__guest_enter)
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ENTRY(__guest_exit)
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/*
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* return convention:
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* guest r0, r1, r2 saved on the stack
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* r0: vcpu pointer
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* r1: exception code
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*/
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add r2, r0, #(VCPU_GUEST_CTXT + USR_REGS_OFFSET + S_R3)
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stm r2!, {r3-r12}
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str lr, [r2, #4]
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add r2, r0, #(VCPU_GUEST_CTXT + USR_REGS_OFFSET + S_R0)
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pop {r3, r4, r5} @ r0, r1, r2
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stm r2, {r3-r5}
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ldr r0, [r0, #VCPU_HOST_CTXT]
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add r0, r0, #(USR_REGS_OFFSET + S_R4)
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ldm r0!, {r4-r12}
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ldr lr, [r0, #4]
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mov r0, r1
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mrs r1, SPSR
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mrs r2, ELR_hyp
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mrc p15, 4, r3, c5, c2, 0 @ HSR
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/*
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* Force loads and stores to complete before unmasking aborts
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* and forcing the delivery of the exception. This gives us a
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* single instruction window, which the handler will try to
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* match.
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*/
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dsb sy
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cpsie a
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.global abort_guest_exit_start
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abort_guest_exit_start:
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isb
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.global abort_guest_exit_end
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abort_guest_exit_end:
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/*
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* If we took an abort, r0[31] will be set, and cmp will set
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* the N bit in PSTATE.
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*/
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cmp r0, #0
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msrmi SPSR_cxsf, r1
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msrmi ELR_hyp, r2
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mcrmi p15, 4, r3, c5, c2, 0 @ HSR
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bx lr
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ENDPROC(__guest_exit)
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/*
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* If VFPv3 support is not available, then we will not switch the VFP
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* registers; however cp10 and cp11 accesses will still trap and fallback
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* to the regular coprocessor emulation code, which currently will
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* inject an undefined exception to the guest.
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*/
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#ifdef CONFIG_VFPv3
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ENTRY(__vfp_guest_restore)
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push {r3, r4, lr}
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@ NEON/VFP used. Turn on VFP access.
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mrc p15, 4, r1, c1, c1, 2 @ HCPTR
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bic r1, r1, #(HCPTR_TCP(10) | HCPTR_TCP(11))
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mcr p15, 4, r1, c1, c1, 2 @ HCPTR
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isb
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@ Switch VFP/NEON hardware state to the guest's
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mov r4, r0
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ldr r0, [r0, #VCPU_HOST_CTXT]
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add r0, r0, #CPU_CTXT_VFP
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bl __vfp_save_state
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add r0, r4, #(VCPU_GUEST_CTXT + CPU_CTXT_VFP)
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bl __vfp_restore_state
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pop {r3, r4, lr}
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pop {r0, r1, r2}
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clrex
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eret
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ENDPROC(__vfp_guest_restore)
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#endif
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.popsection
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