Scott Wood eba5de8dc1 powerpc/fsl-booke-64: Don't limit ppc64_rma_size to one TLB entry ... This is required for kdump to work when loaded at at an address that does not fall within the first TLB entry -- which can easily happen because while the lower limit is enforced via reserved memory, which doesn't affect how much is mapped, the upper limit is enforced via a different mechanism that does. Thus, more TLB entries are needed than would normally be used, as the total memory to be mapped might not be a power of two. Signed-off-by: Scott Wood <scottwood@freescale.com>		2015-10-27 18:13:22 -05:00
..
40x_mmu.c
44x_mmu.c
copro_fault.c	cxl: Move include file cxl.h -> cxl-base.h	2015-06-03 13:27:19 +10:00
dma-noncoherent.c
fault.c	powerpc: Add plain English description for alignment exception oopses	2015-07-06 20:24:35 +10:00
fsl_booke_mmu.c	powerpc/fsl-booke-64: Don't limit ppc64_rma_size to one TLB entry	2015-10-27 18:13:22 -05:00
hash_low_32.S
hash_low_64.S	powerpc/mm: Drop CONFIG_PPC_HAS_HASH_64K	2015-08-18 19:32:10 +10:00
hash_native_64.c	cxl: Move include file cxl.h -> cxl-base.h	2015-06-03 13:27:19 +10:00
hash_utils_64.c	powerpc/mm: Differentiate between hugetlb and THP during page walk	2015-10-12 15:30:09 +11:00
highmem.c	sched/preempt, mm/kmap: Explicitly disable/enable preemption in kmap_atomic_*	2015-05-19 08:39:14 +02:00
hugepage-hash64.c	powerpc/mm: Recompute hash value after a failed update	2015-09-16 22:06:03 +10:00
hugetlbpage-book3e.c
hugetlbpage-hash64.c
hugetlbpage.c	powerpc/mm: Differentiate between hugetlb and THP during page walk	2015-10-12 15:30:09 +11:00
icswx_pid.c
icswx.c
icswx.h
init_32.c
init_64.c
Makefile	powerpc/mmu: Add userspace-to-physical addresses translation cache	2015-06-11 15:16:54 +10:00
mem.c	libnvdimm for 4.3:	2015-09-08 14:35:59 -07:00
mmap.c
mmu_context_hash32.c
mmu_context_hash64.c	powerpc/mmu: Add userspace-to-physical addresses translation cache	2015-06-11 15:16:54 +10:00
mmu_context_iommu.c	powerpc/mmu: Add userspace-to-physical addresses translation cache	2015-06-11 15:16:54 +10:00
mmu_context_nohash.c
mmu_decl.h	powerpc/fsl-booke-64: Don't limit ppc64_rma_size to one TLB entry	2015-10-27 18:13:22 -05:00
numa.c	powerpc/numa: Use of_get_next_parent to simplify code	2015-10-15 20:32:00 +11:00
pgtable_32.c
pgtable_64.c	powerpc/booke64: Move mb() to __set_pte_at() with kernel-addr test	2015-08-07 23:00:01 -05:00
pgtable.c
ppc_mmu_32.c
slb_low.S
slb.c	powerpc/slb: Use a local to avoid multiple calls to get_slb_shadow()	2015-10-01 16:52:01 +10:00
slice.c
subpage-prot.c
tlb_hash32.c
tlb_hash64.c	powerpc/mm: Differentiate between hugetlb and THP during page walk	2015-10-12 15:30:09 +11:00
tlb_low_64e.S	powerpc/e6500: hw tablewalk: optimize a bit for tcd lock acquiring codes	2015-08-17 18:53:47 -05:00
tlb_nohash_low.S	powerpc/85xx: Load all early TLB entries at once	2015-10-22 22:50:46 -05:00
tlb_nohash.c	powerpc/fsl-booke-64: Don't limit ppc64_rma_size to one TLB entry	2015-10-27 18:13:22 -05:00
vphn.c
vphn.h