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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e0082698b6
If PHY is suspended by the time we want to issue ULPI transfers, we will observe timeouts on the ULPI interface. In order to avoid such issue, let's make sure PHY is resumed before issuing a ULPI transfer. Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
104 lines
2.3 KiB
C
104 lines
2.3 KiB
C
/**
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* ulpi.c - DesignWare USB3 Controller's ULPI PHY interface
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*
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* Copyright (C) 2015 Intel Corporation
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*
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* Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/ulpi/regs.h>
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#include "core.h"
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#include "io.h"
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#define DWC3_ULPI_ADDR(a) \
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((a >= ULPI_EXT_VENDOR_SPECIFIC) ? \
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DWC3_GUSB2PHYACC_ADDR(ULPI_ACCESS_EXTENDED) | \
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DWC3_GUSB2PHYACC_EXTEND_ADDR(a) : DWC3_GUSB2PHYACC_ADDR(a))
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static int dwc3_ulpi_busyloop(struct dwc3 *dwc)
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{
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unsigned count = 1000;
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u32 reg;
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while (count--) {
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
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if (!(reg & DWC3_GUSB2PHYACC_BUSY))
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return 0;
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cpu_relax();
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}
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return -ETIMEDOUT;
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}
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static int dwc3_ulpi_read(struct device *dev, u8 addr)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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u32 reg;
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int ret;
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
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reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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}
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reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
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ret = dwc3_ulpi_busyloop(dwc);
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if (ret)
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return ret;
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYACC(0));
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return DWC3_GUSB2PHYACC_DATA(reg);
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}
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static int dwc3_ulpi_write(struct device *dev, u8 addr, u8 val)
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{
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struct dwc3 *dwc = dev_get_drvdata(dev);
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u32 reg;
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reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
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if (reg & DWC3_GUSB2PHYCFG_SUSPHY) {
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reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
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}
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reg = DWC3_GUSB2PHYACC_NEWREGREQ | DWC3_ULPI_ADDR(addr);
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reg |= DWC3_GUSB2PHYACC_WRITE | val;
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dwc3_writel(dwc->regs, DWC3_GUSB2PHYACC(0), reg);
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return dwc3_ulpi_busyloop(dwc);
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}
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static const struct ulpi_ops dwc3_ulpi_ops = {
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.read = dwc3_ulpi_read,
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.write = dwc3_ulpi_write,
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};
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int dwc3_ulpi_init(struct dwc3 *dwc)
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{
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/* Register the interface */
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dwc->ulpi = ulpi_register_interface(dwc->dev, &dwc3_ulpi_ops);
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if (IS_ERR(dwc->ulpi)) {
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dev_err(dwc->dev, "failed to register ULPI interface");
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return PTR_ERR(dwc->ulpi);
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}
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return 0;
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}
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void dwc3_ulpi_exit(struct dwc3 *dwc)
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{
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if (dwc->ulpi) {
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ulpi_unregister_interface(dwc->ulpi);
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dwc->ulpi = NULL;
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}
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}
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