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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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43a6a7e710
Add mt2701 platform driver implementation for playback and capture. The implement follow DAPM structure (memory interface as FE and I2S as BE). Because of the hardware design, i2s out required to be enabled when we need to enable i2s in. This patch includes the implementation. Signed-off-by: Garlic Tseng <garlic.tseng@mediatek.com> Signed-off-by: Mark Brown <broonie@kernel.org>
173 lines
3.8 KiB
C
173 lines
3.8 KiB
C
/*
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* mt2701-afe-common.h -- Mediatek 2701 audio driver definitions
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*
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* Copyright (c) 2016 MediaTek Inc.
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* Author: Garlic Tseng <garlic.tseng@mediatek.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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* only version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#ifndef _MT_2701_AFE_COMMON_H_
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#define _MT_2701_AFE_COMMON_H_
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#include <sound/soc.h>
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#include <linux/clk.h>
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#include <linux/regmap.h>
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#include "mt2701-reg.h"
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#include "../common/mtk-base-afe.h"
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#define MT2701_STREAM_DIR_NUM (SNDRV_PCM_STREAM_LAST + 1)
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#define MT2701_PLL_DOMAIN_0_RATE 98304000
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#define MT2701_PLL_DOMAIN_1_RATE 90316800
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#define MT2701_AUD_AUD_MUX1_DIV_RATE (MT2701_PLL_DOMAIN_0_RATE / 2)
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#define MT2701_AUD_AUD_MUX2_DIV_RATE (MT2701_PLL_DOMAIN_1_RATE / 2)
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enum {
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MT2701_I2S_1,
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MT2701_I2S_2,
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MT2701_I2S_3,
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MT2701_I2S_4,
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MT2701_I2S_NUM,
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};
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enum {
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MT2701_MEMIF_DL1,
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MT2701_MEMIF_DL2,
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MT2701_MEMIF_DL3,
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MT2701_MEMIF_DL4,
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MT2701_MEMIF_DL5,
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MT2701_MEMIF_DL_SINGLE_NUM,
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MT2701_MEMIF_DLM = MT2701_MEMIF_DL_SINGLE_NUM,
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MT2701_MEMIF_UL1,
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MT2701_MEMIF_UL2,
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MT2701_MEMIF_UL3,
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MT2701_MEMIF_UL4,
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MT2701_MEMIF_UL5,
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MT2701_MEMIF_DLBT,
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MT2701_MEMIF_ULBT,
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MT2701_MEMIF_NUM,
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MT2701_IO_I2S = MT2701_MEMIF_NUM,
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MT2701_IO_2ND_I2S,
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MT2701_IO_3RD_I2S,
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MT2701_IO_4TH_I2S,
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MT2701_IO_5TH_I2S,
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MT2701_IO_6TH_I2S,
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MT2701_IO_MRG,
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};
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enum {
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MT2701_IRQ_ASYS_START,
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MT2701_IRQ_ASYS_IRQ1 = MT2701_IRQ_ASYS_START,
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MT2701_IRQ_ASYS_IRQ2,
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MT2701_IRQ_ASYS_IRQ3,
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MT2701_IRQ_ASYS_END,
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};
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/* 2701 clock def */
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enum audio_system_clock_type {
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MT2701_AUD_INFRA_SYS_AUDIO,
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MT2701_AUD_AUD_MUX1_SEL,
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MT2701_AUD_AUD_MUX2_SEL,
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MT2701_AUD_AUD_MUX1_DIV,
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MT2701_AUD_AUD_MUX2_DIV,
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MT2701_AUD_AUD_48K_TIMING,
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MT2701_AUD_AUD_44K_TIMING,
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MT2701_AUD_AUDPLL_MUX_SEL,
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MT2701_AUD_APLL_SEL,
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MT2701_AUD_AUD1PLL_98M,
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MT2701_AUD_AUD2PLL_90M,
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MT2701_AUD_HADDS2PLL_98M,
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MT2701_AUD_HADDS2PLL_294M,
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MT2701_AUD_AUDPLL,
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MT2701_AUD_AUDPLL_D4,
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MT2701_AUD_AUDPLL_D8,
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MT2701_AUD_AUDPLL_D16,
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MT2701_AUD_AUDPLL_D24,
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MT2701_AUD_AUDINTBUS,
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MT2701_AUD_CLK_26M,
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MT2701_AUD_SYSPLL1_D4,
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MT2701_AUD_AUD_K1_SRC_SEL,
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MT2701_AUD_AUD_K2_SRC_SEL,
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MT2701_AUD_AUD_K3_SRC_SEL,
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MT2701_AUD_AUD_K4_SRC_SEL,
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MT2701_AUD_AUD_K5_SRC_SEL,
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MT2701_AUD_AUD_K6_SRC_SEL,
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MT2701_AUD_AUD_K1_SRC_DIV,
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MT2701_AUD_AUD_K2_SRC_DIV,
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MT2701_AUD_AUD_K3_SRC_DIV,
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MT2701_AUD_AUD_K4_SRC_DIV,
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MT2701_AUD_AUD_K5_SRC_DIV,
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MT2701_AUD_AUD_K6_SRC_DIV,
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MT2701_AUD_AUD_I2S1_MCLK,
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MT2701_AUD_AUD_I2S2_MCLK,
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MT2701_AUD_AUD_I2S3_MCLK,
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MT2701_AUD_AUD_I2S4_MCLK,
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MT2701_AUD_AUD_I2S5_MCLK,
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MT2701_AUD_AUD_I2S6_MCLK,
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MT2701_AUD_ASM_M_SEL,
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MT2701_AUD_ASM_H_SEL,
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MT2701_AUD_UNIVPLL2_D4,
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MT2701_AUD_UNIVPLL2_D2,
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MT2701_AUD_SYSPLL_D5,
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MT2701_CLOCK_NUM
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};
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static const unsigned int mt2701_afe_backup_list[] = {
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AUDIO_TOP_CON0,
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AUDIO_TOP_CON4,
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AUDIO_TOP_CON5,
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ASYS_TOP_CON,
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AFE_CONN0,
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AFE_CONN1,
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AFE_CONN2,
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AFE_CONN3,
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AFE_CONN15,
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AFE_CONN16,
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AFE_CONN17,
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AFE_CONN18,
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AFE_CONN19,
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AFE_CONN20,
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AFE_CONN21,
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AFE_CONN22,
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AFE_DAC_CON0,
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AFE_MEMIF_PBUF_SIZE,
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};
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struct snd_pcm_substream;
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struct mtk_base_irq_data;
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struct mt2701_i2s_data {
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int i2s_ctrl_reg;
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int i2s_pwn_shift;
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int i2s_asrc_fs_shift;
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int i2s_asrc_fs_mask;
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};
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enum mt2701_i2s_dir {
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I2S_OUT,
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I2S_IN,
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I2S_DIR_NUM,
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};
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struct mt2701_i2s_path {
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int dai_id;
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int mclk_rate;
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int on[I2S_DIR_NUM];
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int occupied[I2S_DIR_NUM];
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const struct mt2701_i2s_data *i2s_data[2];
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};
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struct mt2701_afe_private {
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struct clk *clocks[MT2701_CLOCK_NUM];
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struct mt2701_i2s_path i2s_path[MT2701_I2S_NUM];
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bool mrg_enable[MT2701_STREAM_DIR_NUM];
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};
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#endif
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