Daniel Borkmann 34b8ab091f bpf, arm64: use more scalable stadd over ldxr / stxr loop in xadd ... Since ARMv8.1 supplement introduced LSE atomic instructions back in 2016, lets add support for STADD and use that in favor of LDXR / STXR loop for the XADD mapping if available. STADD is encoded as an alias for LDADD with XZR as the destination register, therefore add LDADD to the instruction encoder along with STADD as special case and use it in the JIT for CPUs that advertise LSE atomics in CPUID register. If immediate offset in the BPF XADD insn is 0, then use dst register directly instead of temporary one. Signed-off-by: Daniel Borkmann <daniel@iogearbox.net> Acked-by: Jean-Philippe Brucker <jean-philippe.brucker@arm.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Alexei Starovoitov <ast@kernel.org>		2019-04-26 18:53:40 -07:00
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bpf_jit_comp.c	bpf, arm64: use more scalable stadd over ldxr / stxr loop in xadd	2019-04-26 18:53:40 -07:00
bpf_jit.h	bpf, arm64: use more scalable stadd over ldxr / stxr loop in xadd	2019-04-26 18:53:40 -07:00
Makefile	arm64: eBPF JIT compiler	2014-09-08 14:39:21 +01:00