Thor Thayer eb12511f0d fpga: altera-cvp: Discover Vendor Specific offset ... Newer Intel FPGAs have different Vendor Specific offsets than legacy parts. Use PCI discovery to find the CvP registers. Since the register positions remain the same, change the hard coded address to a more flexible way of indexing registers from the offset. Adding new PCI read and write abstraction functions to handle the offset (altera_read_config_dword() and altera_write_config_dword()). Signed-off-by: Thor Thayer <thor.thayer@linux.intel.com> Signed-off-by: Moritz Fischer <mdf@kernel.org>		2019-08-24 11:38:24 -07:00
..
altera-cvp.c	fpga: altera-cvp: Discover Vendor Specific offset	2019-08-24 11:38:24 -07:00
altera-fpga2sdram.c
altera-freeze-bridge.c
altera-hps2fpga.c
altera-pr-ip-core-plat.c	fpga: altera-pr-ip: Make alt_pr_unregister function void	2019-07-24 14:11:52 -07:00
altera-pr-ip-core.c	fpga: altera-pr-ip: Make alt_pr_unregister function void	2019-07-24 14:11:52 -07:00
altera-ps-spi.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422	2019-06-05 17:37:15 +02:00
dfl-afu-dma-region.c	mm: add account_locked_vm utility function	2019-07-16 19:23:25 -07:00
dfl-afu-main.c
dfl-afu-region.c
dfl-afu.h
dfl-fme-br.c
dfl-fme-main.c
dfl-fme-mgr.c	fpga: dfl-fme-mgr: fix FME_PR_INTFC_ID register address.	2019-07-03 19:58:58 +02:00
dfl-fme-pr.c	fpga: dfl: fme: align PR buffer size per PR datawidth	2019-07-03 19:58:59 +02:00
dfl-fme-pr.h
dfl-fme-region.c
dfl-fme.h
dfl-pci.c
dfl.c	fpga: dfl: expand minor range when registering chrdev region	2019-05-24 20:32:12 +02:00
dfl.h
fpga-bridge.c
fpga-mgr.c
fpga-region.c
ice40-spi.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 441	2019-06-05 17:37:17 +02:00
Kconfig	drivers: fpga: Kconfig: pedantic cleanups	2019-06-20 10:41:37 +02:00
machxo2-spi.c
Makefile
of-fpga-region.c	drivers: Add generic helper to match by of_node	2019-06-24 05:22:31 +02:00
socfpga-a10.c
socfpga.c
stratix10-soc.c	fpga: stratix10-soc: fix use-after-free on s10_init()	2019-05-24 20:32:12 +02:00
ts73xx-fpga.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285	2019-06-05 17:36:37 +02:00
xilinx-pr-decoupler.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285	2019-06-05 17:36:37 +02:00
xilinx-spi.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 422	2019-06-05 17:37:15 +02:00
zynq-fpga.c	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285	2019-06-05 17:36:37 +02:00
zynqmp-fpga.c	fpga: zynqmp-fpga: Correctly handle error pointer	2019-05-30 07:56:11 -07:00