mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
eafd53d315
Enable the hardware random generator Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
547 lines
12 KiB
Plaintext
547 lines
12 KiB
Plaintext
/*
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* Copyright (c) 2017 Amlogic, Inc. All rights reserved.
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*
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* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/axg-clkc.h>
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/ {
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compatible = "amlogic,meson-axg";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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/* 16 MiB reserved for Hardware ROM Firmware */
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hwrom_reserved: hwrom@0 {
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reg = <0x0 0x0 0x0 0x1000000>;
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no-map;
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};
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/* Alternate 3 MiB reserved for ARM Trusted Firmware (BL31) */
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secmon_reserved: secmon@5000000 {
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reg = <0x0 0x05000000 0x0 0x300000>;
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no-map;
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};
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};
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cpus {
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x1>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x2>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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cpu3: cpu@3 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0x0 0x3>;
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enable-method = "psci";
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next-level-cache = <&l2>;
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};
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l2: l2-cache0 {
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compatible = "cache";
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};
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};
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arm-pmu {
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compatible = "arm,cortex-a53-pmu";
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interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10
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(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
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};
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xtal: xtal-clk {
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compatible = "fixed-clock";
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clock-frequency = <24000000>;
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clock-output-names = "xtal";
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#clock-cells = <0>;
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};
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soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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cbus: bus@ffd00000 {
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compatible = "simple-bus";
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reg = <0x0 0xffd00000 0x0 0x25000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xffd00000 0x0 0x25000>;
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pwm_ab: pwm@1b000 {
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compatible = "amlogic,meson-axg-ee-pwm";
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reg = <0x0 0x1b000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_cd: pwm@1a000 {
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compatible = "amlogic,meson-axg-ee-pwm";
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reg = <0x0 0x1a000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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reset: reset-controller@1004 {
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compatible = "amlogic,meson-axg-reset";
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reg = <0x0 0x01004 0x0 0x9c>;
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#reset-cells = <1>;
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};
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spicc0: spi@13000 {
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compatible = "amlogic,meson-axg-spicc";
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reg = <0x0 0x13000 0x0 0x3c>;
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interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_SPICC0>;
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clock-names = "core";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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spicc1: spi@15000 {
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compatible = "amlogic,meson-axg-spicc";
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reg = <0x0 0x15000 0x0 0x3c>;
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interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clkc CLKID_SPICC1>;
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clock-names = "core";
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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uart_A: serial@24000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
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reg = <0x0 0x24000 0x0 0x18>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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uart_B: serial@23000 {
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compatible = "amlogic,meson-gx-uart", "amlogic,meson-uart";
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reg = <0x0 0x23000 0x0 0x18>;
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interrupts = <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>;
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status = "disabled";
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};
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};
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ethmac: ethernet@ff3f0000 {
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compatible = "amlogic,meson-gxbb-dwmac", "snps,dwmac";
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reg = <0x0 0xff3f0000 0x0 0x10000
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0x0 0xff634540 0x0 0x8>;
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interrupts = <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "macirq";
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_FCLK_DIV2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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status = "disabled";
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};
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gic: interrupt-controller@ffc01000 {
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compatible = "arm,gic-400";
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reg = <0x0 0xffc01000 0 0x1000>,
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<0x0 0xffc02000 0 0x2000>,
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<0x0 0xffc04000 0 0x2000>,
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<0x0 0xffc06000 0 0x2000>;
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interrupt-controller;
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interrupts = <GIC_PPI 9
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(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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#address-cells = <0>;
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};
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hiubus: bus@ff63c000 {
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compatible = "simple-bus";
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reg = <0x0 0xff63c000 0x0 0x1c00>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x1c00>;
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clkc: clock-controller@0 {
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compatible = "amlogic,axg-clkc";
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#clock-cells = <1>;
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reg = <0x0 0x0 0x0 0x320>;
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};
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};
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mailbox: mailbox@ff63dc00 {
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compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
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reg = <0 0xff63dc00 0 0x400>;
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interrupts = <GIC_SPI 208 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 209 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 210 IRQ_TYPE_EDGE_RISING>;
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#mbox-cells = <1>;
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};
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periphs: periphs@ff634000 {
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compatible = "simple-bus";
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reg = <0x0 0xff634000 0x0 0x2000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
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hwrng: rng {
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compatible = "amlogic,meson-rng";
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reg = <0x0 0x18 0x0 0x4>;
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clocks = <&clkc CLKID_RNG0>;
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clock-names = "core";
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};
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pinctrl_periphs: pinctrl@480 {
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compatible = "amlogic,meson-axg-periphs-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio: bank@480 {
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reg = <0x0 0x00480 0x0 0x40>,
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<0x0 0x004e8 0x0 0x14>,
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<0x0 0x00520 0x0 0x14>,
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<0x0 0x00430 0x0 0x3c>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_periphs 0 0 86>;
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};
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eth_rgmii_x_pins: eth-x-rgmii {
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mux {
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groups = "eth_mdio_x",
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"eth_mdc_x",
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"eth_rgmii_rx_clk_x",
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"eth_rx_dv_x",
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"eth_rxd0_x",
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"eth_rxd1_x",
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"eth_rxd2_rgmii",
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"eth_rxd3_rgmii",
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"eth_rgmii_tx_clk",
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"eth_txen_x",
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"eth_txd0_x",
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"eth_txd1_x",
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"eth_txd2_rgmii",
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"eth_txd3_rgmii";
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function = "eth";
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};
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};
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eth_rgmii_y_pins: eth-y-rgmii {
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mux {
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groups = "eth_mdio_y",
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"eth_mdc_y",
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"eth_rgmii_rx_clk_y",
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"eth_rx_dv_y",
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"eth_rxd0_y",
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"eth_rxd1_y",
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"eth_rxd2_rgmii",
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"eth_rxd3_rgmii",
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"eth_rgmii_tx_clk",
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"eth_txen_y",
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"eth_txd0_y",
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"eth_txd1_y",
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"eth_txd2_rgmii",
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"eth_txd3_rgmii";
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function = "eth";
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};
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};
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pwm_a_a_pins: pwm_a_a {
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mux {
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groups = "pwm_a_a";
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function = "pwm_a";
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};
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};
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pwm_a_x18_pins: pwm_a_x18 {
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mux {
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groups = "pwm_a_x18";
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function = "pwm_a";
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};
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};
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pwm_a_x20_pins: pwm_a_x20 {
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mux {
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groups = "pwm_a_x20";
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function = "pwm_a";
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};
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};
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pwm_a_z_pins: pwm_a_z {
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mux {
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groups = "pwm_a_z";
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function = "pwm_a";
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};
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};
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pwm_b_a_pins: pwm_b_a {
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mux {
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groups = "pwm_b_a";
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function = "pwm_b";
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};
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};
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pwm_b_x_pins: pwm_b_x {
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mux {
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groups = "pwm_b_x";
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function = "pwm_b";
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};
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};
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pwm_b_z_pins: pwm_b_z {
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mux {
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groups = "pwm_b_z";
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function = "pwm_b";
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};
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};
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pwm_c_a_pins: pwm_c_a {
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mux {
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groups = "pwm_c_a";
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function = "pwm_c";
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};
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};
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pwm_c_x10_pins: pwm_c_x10 {
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mux {
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groups = "pwm_c_x10";
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function = "pwm_c";
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};
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};
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pwm_c_x17_pins: pwm_c_x17 {
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mux {
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groups = "pwm_c_x17";
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function = "pwm_c";
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};
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};
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pwm_d_x11_pins: pwm_d_x11 {
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mux {
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groups = "pwm_d_x11";
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function = "pwm_d";
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};
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};
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pwm_d_x16_pins: pwm_d_x16 {
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mux {
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groups = "pwm_d_x16";
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function = "pwm_d";
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};
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};
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spi0_pins: spi0 {
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mux {
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groups = "spi0_miso",
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"spi0_mosi",
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"spi0_clk";
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function = "spi0";
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};
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};
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spi0_ss0_pins: spi0_ss0 {
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mux {
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groups = "spi0_ss0";
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function = "spi0";
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};
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};
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spi0_ss1_pins: spi0_ss1 {
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mux {
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groups = "spi0_ss1";
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function = "spi0";
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};
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};
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spi0_ss2_pins: spi0_ss2 {
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mux {
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groups = "spi0_ss2";
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function = "spi0";
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};
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};
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spi1_a_pins: spi1_a {
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mux {
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groups = "spi1_miso_a",
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"spi1_mosi_a",
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"spi1_clk_a";
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function = "spi1";
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};
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};
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spi1_ss0_a_pins: spi1_ss0_a {
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mux {
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groups = "spi1_ss0_a";
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function = "spi1";
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};
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};
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spi1_ss1_pins: spi1_ss1 {
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mux {
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groups = "spi1_ss1";
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function = "spi1";
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};
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};
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spi1_x_pins: spi1_x {
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mux {
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groups = "spi1_miso_x",
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"spi1_mosi_x",
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"spi1_clk_x";
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function = "spi1";
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};
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};
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spi1_ss0_x_pins: spi1_ss0_x {
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mux {
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groups = "spi1_ss0_x";
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function = "spi1";
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};
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};
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};
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};
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sram: sram@fffc0000 {
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compatible = "amlogic,meson-axg-sram", "mmio-sram";
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reg = <0x0 0xfffc0000 0x0 0x20000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0 0x0 0xfffc0000 0x20000>;
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cpu_scp_lpri: scp-shmem@0 {
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compatible = "amlogic,meson-axg-scp-shmem";
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reg = <0x13000 0x400>;
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};
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cpu_scp_hpri: scp-shmem@200 {
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compatible = "amlogic,meson-axg-scp-shmem";
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reg = <0x13400 0x400>;
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};
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};
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aobus: bus@ff800000 {
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compatible = "simple-bus";
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reg = <0x0 0xff800000 0x0 0x100000>;
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
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pinctrl_aobus: pinctrl@14 {
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compatible = "amlogic,meson-axg-aobus-pinctrl";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gpio_ao: bank@14 {
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reg = <0x0 0x00014 0x0 0x8>,
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<0x0 0x0002c 0x0 0x4>,
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<0x0 0x00024 0x0 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 15>;
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};
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remote_input_ao_pins: remote_input_ao {
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mux {
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groups = "remote_input_ao";
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function = "remote_input_ao";
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};
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};
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};
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pwm_AO_ab: pwm@7000 {
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compatible = "amlogic,meson-axg-ao-pwm";
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reg = <0x0 0x07000 0x0 0x20>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pwm_AO_cd: pwm@2000 {
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compatible = "amlogic,axg-ao-pwm";
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reg = <0x0 0x02000 0x0 0x20>;
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#pwm-cells = <3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_AO: serial@3000 {
|
|
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
|
|
reg = <0x0 0x3000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart_AO_B: serial@4000 {
|
|
compatible = "amlogic,meson-gx-uart", "amlogic,meson-ao-uart";
|
|
reg = <0x0 0x4000 0x0 0x18>;
|
|
interrupts = <GIC_SPI 197 IRQ_TYPE_EDGE_RISING>;
|
|
clocks = <&xtal>, <&clkc CLKID_CLK81>, <&xtal>;
|
|
clock-names = "xtal", "pclk", "baud";
|
|
status = "disabled";
|
|
};
|
|
|
|
ir: ir@8000 {
|
|
compatible = "amlogic,meson-gxbb-ir";
|
|
reg = <0x0 0x8000 0x0 0x20>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|