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Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version this program is distributed in the hope that it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 1334 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070033.113240726@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
105 lines
2.6 KiB
C
105 lines
2.6 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* DaVinci Voice Codec Core Interface for TI platforms
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*
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* Copyright (C) 2010 Texas Instruments, Inc
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*
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* Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
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*/
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#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
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#define __LINUX_MFD_DAVINCI_VOICECODEC_H_
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#include <linux/kernel.h>
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#include <linux/platform_device.h>
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#include <linux/mfd/core.h>
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#include <linux/platform_data/edma.h>
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struct regmap;
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/*
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* Register values.
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*/
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#define DAVINCI_VC_PID 0x00
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#define DAVINCI_VC_CTRL 0x04
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#define DAVINCI_VC_INTEN 0x08
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#define DAVINCI_VC_INTSTATUS 0x0c
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#define DAVINCI_VC_INTCLR 0x10
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#define DAVINCI_VC_EMUL_CTRL 0x14
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#define DAVINCI_VC_RFIFO 0x20
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#define DAVINCI_VC_WFIFO 0x24
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#define DAVINCI_VC_FIFOSTAT 0x28
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#define DAVINCI_VC_TST_CTRL 0x2C
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#define DAVINCI_VC_REG05 0x94
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#define DAVINCI_VC_REG09 0xA4
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#define DAVINCI_VC_REG12 0xB0
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/* DAVINCI_VC_CTRL bit fields */
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#define DAVINCI_VC_CTRL_MASK 0x5500
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#define DAVINCI_VC_CTRL_RSTADC BIT(0)
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#define DAVINCI_VC_CTRL_RSTDAC BIT(1)
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#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
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#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
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#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
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#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
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#define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
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#define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
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#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
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#define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
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#define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
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#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
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/* DAVINCI_VC_INT bit fields */
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#define DAVINCI_VC_INT_MASK 0x3F
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#define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
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#define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
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#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
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#define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
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#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
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#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
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/* DAVINCI_VC_REG05 bit fields */
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#define DAVINCI_VC_REG05_PGA_GAIN 0x07
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/* DAVINCI_VC_REG09 bit fields */
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#define DAVINCI_VC_REG09_MUTE 0x40
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#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
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/* DAVINCI_VC_REG12 bit fields */
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#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
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#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
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#define DAVINCI_VC_CELLS 2
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enum davinci_vc_cells {
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DAVINCI_VC_VCIF_CELL,
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DAVINCI_VC_CQ93VC_CELL,
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};
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struct davinci_vcif {
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struct platform_device *pdev;
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u32 dma_tx_channel;
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u32 dma_rx_channel;
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dma_addr_t dma_tx_addr;
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dma_addr_t dma_rx_addr;
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};
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struct davinci_vc {
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/* Device data */
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struct device *dev;
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struct platform_device *pdev;
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struct clk *clk;
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/* Memory resources */
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void __iomem *base;
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struct regmap *regmap;
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/* MFD cells */
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struct mfd_cell cells[DAVINCI_VC_CELLS];
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/* Client devices */
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struct davinci_vcif davinci_vcif;
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};
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#endif
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