AuxXxilium/linux_dsm_epyc7002
1
0
Fork 0
mirror of https://github.com/AuxXxilium/linux_dsm_epyc7002.git synced 2024-12-28 11:18:45 +07:00
Code Issues Actions Packages Projects Releases Wiki Activity
ea90f66f2a
linux_dsm_epyc7002/arch/arm/mach-imx/mach-mx27_3ds.c
Linus Walleij 8cdcd8aeee
spi: imx/fsl-lpspi: Convert to GPIO descriptors 
This converts the two Freescale i.MX SPI drivers
Freescale i.MX (CONFIG_SPI_IMX) and Freescale i.MX LPSPI
(CONFIG_SPI_FSL_LPSPI) to use GPIO descriptors handled in
the SPI core for GPIO chip selects whether defined in
the device tree or a board file.

The reason why both are converted at the same time is
that they were both using the same platform data and
platform device population helpers when using
board files intertwining the code so this gives a cleaner
cut.

The platform device creation was passing a platform data
container from each boardfile down to the driver using
struct spi_imx_master from <linux/platform_data/spi-imx.h>,
but this was only conveying the number of chipselects and
an int * array of the chipselect GPIO numbers.

The imx27 and imx31 platforms had code passing the
now-unused platform data when creating the platform devices,
this has been repurposed to pass around GPIO descriptor
tables. The platform data struct that was just passing an
array of integers and number of chip selects for the GPIO
lines has been removed.

The number of chipselects used to be passed from the board
file, because this number also limits the number of native
chipselects that the platform can use. To deal with this we
just augment the i.MX (CONFIG_SPI_IMX) driver to support 3
chipselects if the platform does not define "num-cs" as a
device property (such as from the device tree). This covers
all the legacy boards as these use <= 3 native chip selects
(or GPIO lines, and in that case the number of chip selects
is determined by the core from the number of available
GPIO lines). Any new boards should use device tree, so
this is a reasonable simplification to cover all old
boards.

The LPSPI driver never assigned the number of chipselects
and thus always fall back to the core default of 1 chip
select if no GPIOs are defined in the device tree.

The Freescale i.MX driver was already partly utilizing
the SPI core to obtain the GPIO numbers from the device tree,
so this completes the transtion to let the core handle all
of it.

All board files and the core i.MX boardfile registration
code is augmented to account for these changes.

This has been compile-tested with the imx_v4_v5_defconfig
and the imx_v6_v7_defconfig.

Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Shawn Guo <shawnguo@kernel.org>
Cc: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Cc: Robin Gong <yibin.gong@nxp.com>
Cc: Trent Piepho <tpiepho@impinj.com>
Cc: Clark Wang <xiaoning.wang@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Pengutronix Kernel Team <kernel@pengutronix.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
Link: https://lore.kernel.org/r/20200625200252.207614-1-linus.walleij@linaro.org
Signed-off-by: Mark Brown <broonie@kernel.org>
2020-07-13 18:27:06 +01:00

471 lines
11 KiB
C
Raw Blame History

// SPDX-License-Identifier: GPL-2.0-or-later
/*
* Copyright 2009 Freescale Semiconductor, Inc. All Rights Reserved.
*
* Author: Fabio Estevam <fabio.estevam@freescale.com>
*/
/*
* This machine is known as:
* - i.MX27 3-Stack Development System
* - i.MX27 Platform Development Kit (i.MX27 PDK)
*/
#include <linux/platform_device.h>
#include <linux/gpio.h>
#include <linux/gpio/machine.h>
#include <linux/irq.h>
#include <linux/usb/otg.h>
#include <linux/usb/ulpi.h>
#include <linux/delay.h>
#include <linux/mfd/mc13783.h>
#include <linux/spi/spi.h>
#include <linux/regulator/machine.h>
#include <asm/mach-types.h>
#include <asm/mach/arch.h>
#include <asm/mach/time.h>
#include "3ds_debugboard.h"
#include "common.h"
#include "devices-imx27.h"
#include "ehci.h"
#include "hardware.h"
#include "iomux-mx27.h"
#include "ulpi.h"
#define SD1_EN_GPIO IMX_GPIO_NR(2, 25)
#define OTG_PHY_RESET_GPIO IMX_GPIO_NR(2, 23)
#define SPI2_SS0 IMX_GPIO_NR(4, 21)
#define PMIC_INT IMX_GPIO_NR(3, 14)
#define SPI1_SS0 IMX_GPIO_NR(4, 28)
#define SD1_CD IMX_GPIO_NR(2, 26)
#define LCD_RESET IMX_GPIO_NR(1, 3)
#define LCD_ENABLE IMX_GPIO_NR(1, 31)
static const int mx27pdk_pins[] __initconst = {
/* UART1 */
PE12_PF_UART1_TXD,
PE13_PF_UART1_RXD,
PE14_PF_UART1_CTS,
PE15_PF_UART1_RTS,
/* FEC */
PD0_AIN_FEC_TXD0,
PD1_AIN_FEC_TXD1,
PD2_AIN_FEC_TXD2,
PD3_AIN_FEC_TXD3,
PD4_AOUT_FEC_RX_ER,
PD5_AOUT_FEC_RXD1,
PD6_AOUT_FEC_RXD2,
PD7_AOUT_FEC_RXD3,
PD8_AF_FEC_MDIO,
PD9_AIN_FEC_MDC,
PD10_AOUT_FEC_CRS,
PD11_AOUT_FEC_TX_CLK,
PD12_AOUT_FEC_RXD0,
PD13_AOUT_FEC_RX_DV,
PD14_AOUT_FEC_RX_CLK,
PD15_AOUT_FEC_COL,
PD16_AIN_FEC_TX_ER,
PF23_AIN_FEC_TX_EN,
/* SDHC1 */
PE18_PF_SD1_D0,
PE19_PF_SD1_D1,
PE20_PF_SD1_D2,
PE21_PF_SD1_D3,
PE22_PF_SD1_CMD,
PE23_PF_SD1_CLK,
SD1_EN_GPIO | GPIO_GPIO | GPIO_OUT,
/* OTG */
OTG_PHY_RESET_GPIO | GPIO_GPIO | GPIO_OUT,
PC7_PF_USBOTG_DATA5,
PC8_PF_USBOTG_DATA6,
PC9_PF_USBOTG_DATA0,
PC10_PF_USBOTG_DATA2,
PC11_PF_USBOTG_DATA1,
PC12_PF_USBOTG_DATA4,
PC13_PF_USBOTG_DATA3,
PE0_PF_USBOTG_NXT,
PE1_PF_USBOTG_STP,
PE2_PF_USBOTG_DIR,
PE24_PF_USBOTG_CLK,
PE25_PF_USBOTG_DATA7,
/* CSPI1 */
PD31_PF_CSPI1_MOSI,
PD30_PF_CSPI1_MISO,
PD29_PF_CSPI1_SCLK,
PD25_PF_CSPI1_RDY,
SPI1_SS0 | GPIO_GPIO | GPIO_OUT,
/* CSPI2 */
PD22_PF_CSPI2_SCLK,
PD23_PF_CSPI2_MISO,
PD24_PF_CSPI2_MOSI,
SPI2_SS0 | GPIO_GPIO | GPIO_OUT,
/* I2C1 */
PD17_PF_I2C_DATA,
PD18_PF_I2C_CLK,
/* PMIC INT */
PMIC_INT | GPIO_GPIO | GPIO_IN,
/* LCD */
PA5_PF_LSCLK,
PA6_PF_LD0,
PA7_PF_LD1,
PA8_PF_LD2,
PA9_PF_LD3,
PA10_PF_LD4,
PA11_PF_LD5,
PA12_PF_LD6,
PA13_PF_LD7,
PA14_PF_LD8,
PA15_PF_LD9,
PA16_PF_LD10,
PA17_PF_LD11,
PA18_PF_LD12,
PA19_PF_LD13,
PA20_PF_LD14,
PA21_PF_LD15,
PA22_PF_LD16,
PA23_PF_LD17,
PA28_PF_HSYNC,
PA29_PF_VSYNC,
PA30_PF_CONTRAST,
LCD_ENABLE | GPIO_GPIO | GPIO_OUT,
LCD_RESET | GPIO_GPIO | GPIO_OUT,
/* SSI4 */
PC16_PF_SSI4_FS,
PC17_PF_SSI4_RXD,
PC18_PF_SSI4_TXD,
PC19_PF_SSI4_CLK,
};
static const struct imxuart_platform_data uart_pdata __initconst = {
.flags = IMXUART_HAVE_RTSCTS,
};
/*
* Matrix keyboard
*/
static const uint32_t mx27_3ds_keymap[] = {
KEY(0, 0, KEY_UP),
KEY(0, 1, KEY_DOWN),
KEY(1, 0, KEY_RIGHT),
KEY(1, 1, KEY_LEFT),
KEY(1, 2, KEY_ENTER),
KEY(2, 0, KEY_F6),
KEY(2, 1, KEY_F8),
KEY(2, 2, KEY_F9),
KEY(2, 3, KEY_F10),
};
static const struct matrix_keymap_data mx27_3ds_keymap_data __initconst = {
.keymap = mx27_3ds_keymap,
.keymap_size = ARRAY_SIZE(mx27_3ds_keymap),
};
static int mx27_3ds_sdhc1_init(struct device *dev, irq_handler_t detect_irq,
void *data)
{
return request_irq(gpio_to_irq(SD1_CD), detect_irq,
IRQF_TRIGGER_FALLING | IRQF_TRIGGER_RISING, "sdhc1-card-detect", data);
}
static void mx27_3ds_sdhc1_exit(struct device *dev, void *data)
{
free_irq(gpio_to_irq(SD1_CD), data);
}
static const struct imxmmc_platform_data sdhc1_pdata __initconst = {
.init = mx27_3ds_sdhc1_init,
.exit = mx27_3ds_sdhc1_exit,
};
static void mx27_3ds_sdhc1_enable_level_translator(void)
{
/* Turn on TXB0108 OE pin */
gpio_request(SD1_EN_GPIO, "sd1_enable");
gpio_direction_output(SD1_EN_GPIO, 1);
}
static int otg_phy_init(void)
{
gpio_request(OTG_PHY_RESET_GPIO, "usb-otg-reset");
gpio_direction_output(OTG_PHY_RESET_GPIO, 0);
mdelay(1);
gpio_set_value(OTG_PHY_RESET_GPIO, 1);
return 0;
}
static int mx27_3ds_otg_init(struct platform_device *pdev)
{
return mx27_initialize_usb_hw(pdev->id, MXC_EHCI_INTERFACE_DIFF_UNI);
}
static struct mxc_usbh_platform_data otg_pdata __initdata = {
.init = mx27_3ds_otg_init,
.portsc = MXC_EHCI_MODE_ULPI,
};
static const struct fsl_usb2_platform_data otg_device_pdata __initconst = {
.operating_mode = FSL_USB2_DR_DEVICE,
.phy_mode = FSL_USB2_PHY_ULPI,
};
static bool otg_mode_host __initdata;
static int __init mx27_3ds_otg_mode(char *options)
{
if (!strcmp(options, "host"))
otg_mode_host = true;
else if (!strcmp(options, "device"))
otg_mode_host = false;
else
pr_info("otg_mode neither \"host\" nor \"device\". "
"Defaulting to device\n");
return 1;
}
__setup("otg_mode=", mx27_3ds_otg_mode);
/* Regulators */
static struct regulator_init_data gpo_init = {
.constraints = {
.boot_on = 1,
.always_on = 1,
}
};
static struct regulator_consumer_supply vmmc1_consumers[] = {
REGULATOR_SUPPLY("vcore", "spi0.0"),
};
static struct regulator_init_data vmmc1_init = {
.constraints = {
.min_uV = 2800000,
.max_uV = 2800000,
.apply_uV = 1,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE |
REGULATOR_CHANGE_STATUS,
},
.num_consumer_supplies = ARRAY_SIZE(vmmc1_consumers),
.consumer_supplies = vmmc1_consumers,
};
static struct regulator_consumer_supply vgen_consumers[] = {
REGULATOR_SUPPLY("vdd", "spi0.0"),
};
static struct regulator_init_data vgen_init = {
.constraints = {
.min_uV = 1800000,
.max_uV = 1800000,
.valid_ops_mask = REGULATOR_CHANGE_VOLTAGE,
},
.num_consumer_supplies = ARRAY_SIZE(vgen_consumers),
.consumer_supplies = vgen_consumers,
};
static struct mc13xxx_regulator_init_data mx27_3ds_regulators[] = {
{
.id = MC13783_REG_VMMC1,
.init_data = &vmmc1_init,
}, {
.id = MC13783_REG_VGEN,
.init_data = &vgen_init,
}, {
.id = MC13783_REG_GPO1, /* Turn on 1.8V */
.init_data = &gpo_init,
}, {
.id = MC13783_REG_GPO3, /* Turn on 3.3V */
.init_data = &gpo_init,
},
};
/* MC13783 */
static struct mc13xxx_codec_platform_data mx27_3ds_codec = {
.dac_ssi_port = MC13783_SSI1_PORT,
.adc_ssi_port = MC13783_SSI1_PORT,
};
static struct mc13xxx_platform_data mc13783_pdata = {
.regulators = {
.regulators = mx27_3ds_regulators,
.num_regulators = ARRAY_SIZE(mx27_3ds_regulators),
},
.flags = MC13XXX_USE_TOUCHSCREEN | MC13XXX_USE_RTC |
MC13XXX_USE_CODEC,
.codec = &mx27_3ds_codec,
};
static struct imx_ssi_platform_data mx27_3ds_ssi_pdata = {
.flags = IMX_SSI_DMA | IMX_SSI_NET,
};
/* SPI */
static struct gpiod_lookup_table mx27_spi1_gpiod_table = {
.dev_id = "imx27-cspi.0", /* Actual device name for spi1 */
.table = {
/*
* The i.MX27 has the i.MX21 GPIO controller, the SPI1 CS GPIO
* SPI1_SS0 is numbered IMX_GPIO_NR(4, 28).
*
* This is in "bank 4" which is subtracted by one in the macro
* so this is actually bank 3 on "imx21-gpio.3".
*/
GPIO_LOOKUP_IDX("imx21-gpio.3", 28, "cs", 0, GPIO_ACTIVE_LOW),
{ },
},
};
static struct gpiod_lookup_table mx27_spi2_gpiod_table = {
.dev_id = "imx27-cspi.1", /* Actual device name for spi2 */
.table = {
/*
* The i.MX27 has the i.MX21 GPIO controller, the SPI2 CS GPIO
* SPI2_SS0 is numbered IMX_GPIO_NR(4, 21).
*
* This is in "bank 4" which is subtracted by one in the macro
* so this is actually bank 3 on "imx21-gpio.3".
*/
GPIO_LOOKUP_IDX("imx21-gpio.3", 21, "cs", 0, GPIO_ACTIVE_LOW),
{ },
},
};
static struct imx_fb_videomode mx27_3ds_modes[] = {
{ /* 480x640 @ 60 Hz */
.mode = {
.name = "Epson-VGA",
.refresh = 60,
.xres = 480,
.yres = 640,
.pixclock = 41701,
.left_margin = 20,
.right_margin = 41,
.upper_margin = 10,
.lower_margin = 5,
.hsync_len = 20,
.vsync_len = 10,
.sync = FB_SYNC_OE_ACT_HIGH |
FB_SYNC_CLK_INVERT,
.vmode = FB_VMODE_NONINTERLACED,
.flag = 0,
},
.bpp = 16,
.pcr = 0xFAC08B82,
},
};
static const struct imx_fb_platform_data mx27_3ds_fb_data __initconst = {
.mode = mx27_3ds_modes,
.num_modes = ARRAY_SIZE(mx27_3ds_modes),
.pwmr = 0x00A903FF,
.lscr1 = 0x00120300,
.dmacr = 0x00020010,
};
/* LCD */
static struct gpiod_lookup_table mx27_3ds_lcd_gpiod_table = {
.dev_id = "spi0.0", /* Bus 0 chipselect 0 */
.table = {
/*
* The i.MX27 has the i.MX21 GPIO controller, the GPIOs
* numbered IMX_GPIO_NR(1, 3) and IMX_GPIO_NR(1, 31)
* are in "bank 1" which is subtracted by one in the macro
* so these are actually bank 0 on "imx21-gpio.0".
*/
GPIO_LOOKUP("imx21-gpio.0", 3, "reset", GPIO_ACTIVE_HIGH),
GPIO_LOOKUP("imx21-gpio.0", 31, "enable", GPIO_ACTIVE_HIGH),
{ },
},
};
static struct spi_board_info mx27_3ds_spi_devs[] __initdata = {
{
.modalias = "mc13783",
.max_speed_hz = 1000000,
.bus_num = 1,
.chip_select = 0, /* SS0 */
.platform_data = &mc13783_pdata,
/* irq number is run-time assigned */
.mode = SPI_CS_HIGH,
}, {
.modalias = "l4f00242t03",
.max_speed_hz = 5000000,
.bus_num = 0,
.chip_select = 0, /* SS0 */
},
};
static const struct imxi2c_platform_data mx27_3ds_i2c0_data __initconst = {
.bitrate = 100000,
};
static void __init mx27pdk_init(void)
{
imx27_soc_init();
mxc_gpio_setup_multiple_pins(mx27pdk_pins, ARRAY_SIZE(mx27pdk_pins),
"mx27pdk");
imx27_add_imx_uart0(&uart_pdata);
imx27_add_fec(NULL);
imx27_add_imx_keypad(&mx27_3ds_keymap_data);
imx27_add_imx2_wdt();
imx27_add_spi_imx1(&mx27_spi2_gpiod_table);
imx27_add_spi_imx0(&mx27_spi1_gpiod_table);
imx27_add_imx_i2c(0, &mx27_3ds_i2c0_data);
imx27_add_imx_fb(&mx27_3ds_fb_data);
imx27_add_imx_ssi(0, &mx27_3ds_ssi_pdata);
}
static void __init mx27pdk_late_init(void)
{
mx27_3ds_sdhc1_enable_level_translator();
imx27_add_mxc_mmc(0, &sdhc1_pdata);
otg_phy_init();
if (otg_mode_host) {
otg_pdata.otg = imx_otg_ulpi_create(ULPI_OTG_DRVVBUS |
ULPI_OTG_DRVVBUS_EXT);
if (otg_pdata.otg)
imx27_add_mxc_ehci_otg(&otg_pdata);
}
if (!otg_mode_host)
imx27_add_fsl_usb2_udc(&otg_device_pdata);
gpiod_add_lookup_table(&mx27_3ds_lcd_gpiod_table);
mx27_3ds_spi_devs[0].irq = gpio_to_irq(PMIC_INT);
spi_register_board_info(mx27_3ds_spi_devs,
ARRAY_SIZE(mx27_3ds_spi_devs));
if (mxc_expio_init(MX27_CS5_BASE_ADDR, IMX_GPIO_NR(3, 28)))
pr_warn("Init of the debugboard failed, all devices on the debugboard are unusable.\n");
imx_add_platform_device("imx_mc13783", 0, NULL, 0, NULL, 0);
}
static void __init mx27pdk_timer_init(void)
{
mx27_clocks_init(26000000);
}
MACHINE_START(MX27_3DS, "Freescale MX27PDK")
/* maintainer: Freescale Semiconductor, Inc. */
.atag_offset = 0x100,
.map_io = mx27_map_io,
.init_early = imx27_init_early,
.init_irq = mx27_init_irq,
.init_time = mx27pdk_timer_init,
.init_machine = mx27pdk_init,
.init_late = mx27pdk_late_init,
.restart = mxc_restart,
MACHINE_END
Reference in New Issue View Git Blame Copy Permalink