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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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4e461e62fc
Update the "gpio-ranges" property of the CBUS GPIO controller on Meson8b because it only provides 83 GPIOs. The GPIO definitions in include/dt-bindings/gpio/meson8b-gpio.h inherited all GPIOs from Meson8 until recently. However, Meson8b does not support all GPIOs which are supported by Meson8 (Meson8b doesn't have a GPIOZ bank, most of the pins from the GPIODV bank are missing on Meson8b - just to name a few differences). The actual number of GPIOs is only 83, instead of 120 from Meson8 plus the 10 GPIOs from the DIF bank on Meson8b. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Kevin Hilman <khilman@baylibre.com>
356 lines
8.4 KiB
Plaintext
356 lines
8.4 KiB
Plaintext
/*
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* Copyright 2015 Endless Mobile, Inc.
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* Author: Carlo Caione <carlo@endlessm.com>
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*
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* This file is dual-licensed: you can use it either under the terms
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* of the GPL or the X11 license, at your option. Note that this dual
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* licensing only applies to this file, and not this project as a
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* whole.
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*
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* a) This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of the
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* License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*
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* Or, alternatively,
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*
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* b) Permission is hereby granted, free of charge, to any person
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* obtaining a copy of this software and associated documentation
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* files (the "Software"), to deal in the Software without
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* restriction, including without limitation the rights to use,
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* copy, modify, merge, publish, distribute, sublicense, and/or
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* sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following
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* conditions:
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*
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* The above copyright notice and this permission notice shall be
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* included in all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
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* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
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* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
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* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <dt-bindings/clock/meson8b-clkc.h>
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#include <dt-bindings/gpio/meson8b-gpio.h>
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#include <dt-bindings/reset/amlogic,meson8b-reset.h>
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#include <dt-bindings/reset/amlogic,meson8b-clkc-reset.h>
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#include "meson.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@200 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x200>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU0_SOFT_RESET>;
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};
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cpu@201 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x201>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU1_SOFT_RESET>;
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};
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cpu@202 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x202>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU2_SOFT_RESET>;
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};
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cpu@203 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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next-level-cache = <&L2>;
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reg = <0x203>;
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enable-method = "amlogic,meson8b-smp";
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resets = <&clkc CLKC_RESET_CPU3_SOFT_RESET>;
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};
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};
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reserved-memory {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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/* 2 MiB reserved for Hardware ROM Firmware? */
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hwrom@0 {
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reg = <0x0 0x200000>;
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no-map;
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};
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};
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scu@c4300000 {
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compatible = "arm,cortex-a5-scu";
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reg = <0xc4300000 0x100>;
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};
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}; /* end of / */
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&aobus {
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pmu: pmu@e0 {
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compatible = "amlogic,meson8b-pmu", "syscon";
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reg = <0xe0 0x18>;
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};
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pinctrl_aobus: pinctrl@84 {
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compatible = "amlogic,meson8b-aobus-pinctrl";
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reg = <0x84 0xc>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio_ao: ao-bank@14 {
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reg = <0x14 0x4>,
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<0x2c 0x4>,
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<0x24 0x8>;
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reg-names = "mux", "pull", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_aobus 0 0 16>;
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};
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uart_ao_a_pins: uart_ao_a {
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mux {
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groups = "uart_tx_ao_a", "uart_rx_ao_a";
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function = "uart_ao";
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};
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};
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};
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};
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&cbus {
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clkc: clock-controller@4000 {
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#clock-cells = <1>;
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#reset-cells = <1>;
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compatible = "amlogic,meson8b-clkc";
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reg = <0x8000 0x4>, <0x4000 0x460>;
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};
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reset: reset-controller@4404 {
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compatible = "amlogic,meson8b-reset";
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reg = <0x4404 0x9c>;
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#reset-cells = <1>;
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};
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analog_top: analog-top@81a8 {
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compatible = "amlogic,meson8b-analog-top", "syscon";
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reg = <0x81a8 0x14>;
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};
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pwm_ef: pwm@86c0 {
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compatible = "amlogic,meson8b-pwm";
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reg = <0x86c0 0x10>;
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#pwm-cells = <3>;
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status = "disabled";
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};
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pinctrl_cbus: pinctrl@9880 {
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compatible = "amlogic,meson8b-cbus-pinctrl";
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reg = <0x9880 0x10>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio: banks@80b0 {
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reg = <0x80b0 0x28>,
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<0x80e8 0x18>,
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<0x8120 0x18>,
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<0x8030 0x38>;
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reg-names = "mux", "pull", "pull-enable", "gpio";
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gpio-controller;
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#gpio-cells = <2>;
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gpio-ranges = <&pinctrl_cbus 0 0 83>;
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};
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eth_rgmii_pins: eth-rgmii {
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mux {
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groups = "eth_tx_clk",
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"eth_tx_en",
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"eth_txd1_0",
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"eth_txd1_1",
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"eth_txd0_0",
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"eth_txd0_1",
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"eth_rx_clk",
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"eth_rx_dv",
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"eth_rxd1",
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"eth_rxd0",
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"eth_mdio_en",
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"eth_mdc",
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"eth_ref_clk",
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"eth_txd2",
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"eth_txd3";
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function = "ethernet";
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};
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};
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sd_b_pins: sd-b {
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mux {
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groups = "sd_d0_b", "sd_d1_b", "sd_d2_b",
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"sd_d3_b", "sd_clk_b", "sd_cmd_b";
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function = "sd_b";
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};
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};
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};
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};
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&ahb_sram {
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smp-sram@1ff80 {
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compatible = "amlogic,meson8b-smp-sram";
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reg = <0x1ff80 0x8>;
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};
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};
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&efuse {
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compatible = "amlogic,meson8b-efuse";
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clocks = <&clkc CLKID_EFUSE>;
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clock-names = "core";
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};
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ðmac {
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compatible = "amlogic,meson8b-dwmac", "snps,dwmac-3.70a", "snps,dwmac";
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reg = <0xc9410000 0x10000
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0xc1108140 0x4>;
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clocks = <&clkc CLKID_ETH>,
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<&clkc CLKID_MPLL2>,
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<&clkc CLKID_MPLL2>;
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clock-names = "stmmaceth", "clkin0", "clkin1";
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resets = <&reset RESET_ETHERNET>;
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reset-names = "stmmaceth";
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};
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&gpio_intc {
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compatible = "amlogic,meson-gpio-intc",
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"amlogic,meson8b-gpio-intc";
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status = "okay";
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};
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&hwrng {
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compatible = "amlogic,meson8b-rng", "amlogic,meson-rng";
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clocks = <&clkc CLKID_RNG0>;
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clock-names = "core";
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};
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&i2c_AO {
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clocks = <&clkc CLKID_CLK81>;
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};
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&i2c_A {
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clocks = <&clkc CLKID_I2C>;
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};
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&i2c_B {
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clocks = <&clkc CLKID_I2C>;
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};
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&L2 {
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arm,data-latency = <3 3 3>;
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arm,tag-latency = <2 2 2>;
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arm,filter-ranges = <0x100000 0xc0000000>;
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prefetch-data = <1>;
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prefetch-instr = <1>;
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arm,shared-override;
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};
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&pwm_ab {
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compatible = "amlogic,meson8b-pwm";
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};
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&pwm_cd {
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compatible = "amlogic,meson8b-pwm";
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};
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&saradc {
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compatible = "amlogic,meson8b-saradc", "amlogic,meson-saradc";
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clocks = <&clkc CLKID_XTAL>,
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<&clkc CLKID_SAR_ADC>;
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clock-names = "clkin", "core";
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};
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&sdio {
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compatible = "amlogic,meson8b-sdio", "amlogic,meson-mx-sdio";
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clocks = <&clkc CLKID_SDIO>, <&clkc CLKID_CLK81>;
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clock-names = "core", "clkin";
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};
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&uart_AO {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_CLK81>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_A {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART0>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_B {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART1>;
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clock-names = "baud", "xtal", "pclk";
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};
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&uart_C {
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compatible = "amlogic,meson8b-uart", "amlogic,meson-uart";
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clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_XTAL>, <&clkc CLKID_UART2>;
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clock-names = "baud", "xtal", "pclk";
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};
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&usb0 {
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compatible = "amlogic,meson8b-usb", "snps,dwc2";
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clocks = <&clkc CLKID_USB0_DDR_BRIDGE>;
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clock-names = "otg";
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};
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&usb1 {
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compatible = "amlogic,meson8b-usb", "snps,dwc2";
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clocks = <&clkc CLKID_USB1_DDR_BRIDGE>;
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clock-names = "otg";
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};
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&usb0_phy {
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compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
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clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB0>;
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clock-names = "usb_general", "usb";
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resets = <&reset RESET_USB_OTG>;
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};
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&usb1_phy {
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compatible = "amlogic,meson8b-usb2-phy", "amlogic,meson-mx-usb2-phy";
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clocks = <&clkc CLKID_USB>, <&clkc CLKID_USB1>;
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clock-names = "usb_general", "usb";
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resets = <&reset RESET_USB_OTG>;
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};
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&wdt {
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compatible = "amlogic,meson8b-wdt";
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};
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