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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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368dd5acd1
Implement the Panasonic MN10300 AM34 CPU subarch and implement SMP support for MN10300. Also implement support for the MN2WS0060 processor and the ASB2364 evaluation board which are AM34 based. Signed-off-by: Akira Takeuchi <takeuchi.akr@jp.panasonic.com> Signed-off-by: Kiyoshi Owada <owada.kiyoshi@jp.panasonic.com> Signed-off-by: David Howells <dhowells@redhat.com>
104 lines
4.7 KiB
C
104 lines
4.7 KiB
C
/* MN2WS0050 on-board DMA controller registers
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*
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* Copyright (C) 2002 Red Hat, Inc. All Rights Reserved.
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* Written by David Howells (dhowells@redhat.com)
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*/
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#ifndef _ASM_PROC_DMACTL_REGS_H
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#define _ASM_PROC_DMACTL_REGS_H
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#include <asm/cpu-regs.h>
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#ifdef __KERNEL__
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/* DMA registers */
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#define DMxCTR(N) __SYSREG(0xd4005000+(N*0x100), u32) /* control reg */
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#define DMxCTR_BG 0x0000001f /* transfer request source */
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#define DMxCTR_BG_SOFT 0x00000000 /* - software source */
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#define DMxCTR_BG_SC0TX 0x00000002 /* - serial port 0 transmission */
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#define DMxCTR_BG_SC0RX 0x00000003 /* - serial port 0 reception */
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#define DMxCTR_BG_SC1TX 0x00000004 /* - serial port 1 transmission */
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#define DMxCTR_BG_SC1RX 0x00000005 /* - serial port 1 reception */
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#define DMxCTR_BG_SC2TX 0x00000006 /* - serial port 2 transmission */
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#define DMxCTR_BG_SC2RX 0x00000007 /* - serial port 2 reception */
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#define DMxCTR_BG_TM0UFLOW 0x00000008 /* - timer 0 underflow */
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#define DMxCTR_BG_TM1UFLOW 0x00000009 /* - timer 1 underflow */
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#define DMxCTR_BG_TM2UFLOW 0x0000000a /* - timer 2 underflow */
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#define DMxCTR_BG_TM3UFLOW 0x0000000b /* - timer 3 underflow */
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#define DMxCTR_BG_TM6ACMPCAP 0x0000000c /* - timer 6A compare/capture */
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#define DMxCTR_BG_RYBY 0x0000000d /* - NAND Flash RY/BY request source */
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#define DMxCTR_BG_RMC 0x0000000e /* - remote controller output */
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#define DMxCTR_BG_XIRQ12 0x00000011 /* - XIRQ12 pin interrupt source */
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#define DMxCTR_BG_XIRQ13 0x00000012 /* - XIRQ13 pin interrupt source */
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#define DMxCTR_BG_TCK 0x00000014 /* - tick timer underflow */
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#define DMxCTR_BG_SC4TX 0x00000019 /* - serial port4 transmission */
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#define DMxCTR_BG_SC4RX 0x0000001a /* - serial port4 reception */
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#define DMxCTR_BG_SC5TX 0x0000001b /* - serial port5 transmission */
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#define DMxCTR_BG_SC5RX 0x0000001c /* - serial port5 reception */
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#define DMxCTR_BG_SC6TX 0x0000001d /* - serial port6 transmission */
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#define DMxCTR_BG_SC6RX 0x0000001e /* - serial port6 reception */
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#define DMxCTR_BG_TMSUFLOW 0x0000001f /* - timestamp timer underflow */
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#define DMxCTR_SAM 0x00000060 /* DMA transfer src addr mode */
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#define DMxCTR_SAM_INCR 0x00000000 /* - increment */
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#define DMxCTR_SAM_DECR 0x00000020 /* - decrement */
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#define DMxCTR_SAM_FIXED 0x00000040 /* - fixed */
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#define DMxCTR_DAM 0x00000300 /* DMA transfer dest addr mode */
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#define DMxCTR_DAM_INCR 0x00000000 /* - increment */
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#define DMxCTR_DAM_DECR 0x00000100 /* - decrement */
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#define DMxCTR_DAM_FIXED 0x00000200 /* - fixed */
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#define DMxCTR_UT 0x00006000 /* DMA transfer unit */
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#define DMxCTR_UT_1 0x00000000 /* - 1 byte */
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#define DMxCTR_UT_2 0x00002000 /* - 2 byte */
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#define DMxCTR_UT_4 0x00004000 /* - 4 byte */
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#define DMxCTR_UT_16 0x00006000 /* - 16 byte */
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#define DMxCTR_RRE 0x00008000 /* DMA round robin enable */
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#define DMxCTR_TEN 0x00010000 /* DMA channel transfer enable */
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#define DMxCTR_RQM 0x00060000 /* external request input source mode */
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#define DMxCTR_RQM_FALLEDGE 0x00000000 /* - falling edge */
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#define DMxCTR_RQM_RISEEDGE 0x00020000 /* - rising edge */
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#define DMxCTR_RQM_LOLEVEL 0x00040000 /* - low level */
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#define DMxCTR_RQM_HILEVEL 0x00060000 /* - high level */
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#define DMxCTR_RQF 0x01000000 /* DMA transfer request flag */
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#define DMxCTR_PERR 0x40000000 /* DMA transfer parameter error flag */
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#define DMxCTR_XEND 0x80000000 /* DMA transfer end flag */
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#define DMxSRC(N) __SYSREG(0xd4005004+(N*0x100), u32) /* control reg */
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#define DMxDST(N) __SYSREG(0xd4005008+(N*0x100), u32) /* source addr reg */
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#define DMxSIZ(N) __SYSREG(0xd400500c+(N*0x100), u32) /* dest addr reg */
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#define DMxSIZ_CT 0x000fffff /* number of bytes to transfer */
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#define DMxCYC(N) __SYSREG(0xd4005010+(N*0x100), u32) /* intermittent size reg */
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#define DMxCYC_CYC 0x000000ff /* number of interrmittent transfers -1 */
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#define DM0IRQ 16 /* DMA channel 0 complete IRQ */
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#define DM1IRQ 17 /* DMA channel 1 complete IRQ */
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#define DM2IRQ 18 /* DMA channel 2 complete IRQ */
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#define DM3IRQ 19 /* DMA channel 3 complete IRQ */
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#define DM0ICR GxICR(DM0IRQ) /* DMA channel 0 complete intr ctrl reg */
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#define DM1ICR GxICR(DM0IR1) /* DMA channel 1 complete intr ctrl reg */
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#define DM2ICR GxICR(DM0IR2) /* DMA channel 2 complete intr ctrl reg */
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#define DM3ICR GxICR(DM0IR3) /* DMA channel 3 complete intr ctrl reg */
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#ifndef __ASSEMBLY__
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struct mn10300_dmactl_regs {
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u32 ctr;
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const void *src;
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void *dst;
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u32 siz;
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u32 cyc;
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} __attribute__((aligned(0x100)));
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_PROC_DMACTL_REGS_H */
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