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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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ea0588cb6b
Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Rusty Russell <rusty@rustcorp.com.au> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Srivatsa S. Bhat <srivatsa.bhat@linux.vnet.ibm.com> Acked-by: Paul Mundt <lethal@linux-sh.org> Link: http://lkml.kernel.org/r/20120420124557.855203626@linutronix.de
184 lines
4.3 KiB
C
184 lines
4.3 KiB
C
#ifndef __ASM_SH_PROCESSOR_H
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#define __ASM_SH_PROCESSOR_H
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#include <asm/cpu-features.h>
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#include <asm/segment.h>
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#include <asm/cache.h>
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#ifndef __ASSEMBLY__
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/*
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* CPU type and hardware bug flags. Kept separately for each CPU.
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*
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* Each one of these also needs a CONFIG_CPU_SUBTYPE_xxx entry
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* in arch/sh/mm/Kconfig, as well as an entry in arch/sh/kernel/setup.c
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* for parsing the subtype in get_cpu_subtype().
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*/
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enum cpu_type {
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/* SH-2 types */
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CPU_SH7619,
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/* SH-2A types */
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CPU_SH7201, CPU_SH7203, CPU_SH7206, CPU_SH7263, CPU_MXG,
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/* SH-3 types */
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CPU_SH7705, CPU_SH7706, CPU_SH7707,
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CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
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CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
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CPU_SH7720, CPU_SH7721, CPU_SH7729,
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/* SH-4 types */
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CPU_SH7750, CPU_SH7750S, CPU_SH7750R, CPU_SH7751, CPU_SH7751R,
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CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
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/* SH-4A types */
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CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
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CPU_SH7723, CPU_SH7724, CPU_SH7757, CPU_SHX3,
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/* SH4AL-DSP types */
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CPU_SH7343, CPU_SH7722, CPU_SH7366, CPU_SH7372,
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/* SH-5 types */
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CPU_SH5_101, CPU_SH5_103,
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/* Unknown subtype */
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CPU_SH_NONE
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};
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enum cpu_family {
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CPU_FAMILY_SH2,
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CPU_FAMILY_SH2A,
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CPU_FAMILY_SH3,
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CPU_FAMILY_SH4,
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CPU_FAMILY_SH4A,
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CPU_FAMILY_SH4AL_DSP,
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CPU_FAMILY_SH5,
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CPU_FAMILY_UNKNOWN,
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};
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/*
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* TLB information structure
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*
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* Defined for both I and D tlb, per-processor.
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*/
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struct tlb_info {
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unsigned long long next;
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unsigned long long first;
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unsigned long long last;
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unsigned int entries;
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unsigned int step;
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unsigned long flags;
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};
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struct sh_cpuinfo {
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unsigned int type, family;
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int cut_major, cut_minor;
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unsigned long loops_per_jiffy;
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unsigned long asid_cache;
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struct cache_info icache; /* Primary I-cache */
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struct cache_info dcache; /* Primary D-cache */
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struct cache_info scache; /* Secondary cache */
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/* TLB info */
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struct tlb_info itlb;
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struct tlb_info dtlb;
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unsigned int phys_bits;
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unsigned long flags;
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} __attribute__ ((aligned(L1_CACHE_BYTES)));
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extern struct sh_cpuinfo cpu_data[];
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#define boot_cpu_data cpu_data[0]
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#define current_cpu_data cpu_data[smp_processor_id()]
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#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
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#define cpu_sleep() __asm__ __volatile__ ("sleep" : : : "memory")
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#define cpu_relax() barrier()
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void default_idle(void);
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void cpu_idle_wait(void);
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void stop_this_cpu(void *);
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/* Forward decl */
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struct seq_operations;
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struct task_struct;
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extern struct pt_regs fake_swapper_regs;
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extern void cpu_init(void);
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extern void cpu_probe(void);
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/* arch/sh/kernel/process.c */
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extern unsigned int xstate_size;
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extern void free_thread_xstate(struct task_struct *);
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extern struct kmem_cache *task_xstate_cachep;
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/* arch/sh/mm/alignment.c */
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extern int get_unalign_ctl(struct task_struct *, unsigned long addr);
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extern int set_unalign_ctl(struct task_struct *, unsigned int val);
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#define GET_UNALIGN_CTL(tsk, addr) get_unalign_ctl((tsk), (addr))
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#define SET_UNALIGN_CTL(tsk, val) set_unalign_ctl((tsk), (val))
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/* arch/sh/mm/init.c */
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extern unsigned int mem_init_done;
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/* arch/sh/kernel/setup.c */
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const char *get_cpu_subtype(struct sh_cpuinfo *c);
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extern const struct seq_operations cpuinfo_op;
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/* thread_struct flags */
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#define SH_THREAD_UAC_NOPRINT (1 << 0)
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#define SH_THREAD_UAC_SIGBUS (1 << 1)
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#define SH_THREAD_UAC_MASK (SH_THREAD_UAC_NOPRINT | SH_THREAD_UAC_SIGBUS)
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/* processor boot mode configuration */
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#define MODE_PIN0 (1 << 0)
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#define MODE_PIN1 (1 << 1)
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#define MODE_PIN2 (1 << 2)
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#define MODE_PIN3 (1 << 3)
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#define MODE_PIN4 (1 << 4)
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#define MODE_PIN5 (1 << 5)
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#define MODE_PIN6 (1 << 6)
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#define MODE_PIN7 (1 << 7)
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#define MODE_PIN8 (1 << 8)
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#define MODE_PIN9 (1 << 9)
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#define MODE_PIN10 (1 << 10)
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#define MODE_PIN11 (1 << 11)
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#define MODE_PIN12 (1 << 12)
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#define MODE_PIN13 (1 << 13)
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#define MODE_PIN14 (1 << 14)
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#define MODE_PIN15 (1 << 15)
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int generic_mode_pins(void);
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int test_mode_pin(int pin);
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#ifdef CONFIG_VSYSCALL
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int vsyscall_init(void);
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#else
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#define vsyscall_init() do { } while (0)
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#endif
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/*
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* SH-2A has both 16 and 32-bit opcodes, do lame encoding checks.
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*/
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#ifdef CONFIG_CPU_SH2A
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extern unsigned int instruction_size(unsigned int insn);
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#elif defined(CONFIG_SUPERH32)
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#define instruction_size(insn) (2)
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#else
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#define instruction_size(insn) (4)
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#endif
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#endif /* __ASSEMBLY__ */
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#ifdef CONFIG_SUPERH32
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# include "processor_32.h"
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#else
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# include "processor_64.h"
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#endif
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#endif /* __ASM_SH_PROCESSOR_H */
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