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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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deaf7565eb
The peripheral address space is architectural address window which is uncached and typically used to wire up peripherals. For ARC700 cores (ARCompact ISA based) this was fixed to 1GB region 0xC000_0000 - 0xFFFF_FFFF. For ARCv2 based HS38 cores the start address is flexible and can be 0xC, 0xD, 0xE, 0xF 000_000 by programming AUX_NON_VOLATILE_LIMIT reg (typically done in bootloader) Further in cas of PAE, the physical address can extend beyond 4GB so need to confine this check, otherwise all pages beyond 4GB will be treated as uncached Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
107 lines
2.6 KiB
C
107 lines
2.6 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/mm.h>
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#include <linux/slab.h>
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#include <linux/cache.h>
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static inline bool arc_uncached_addr_space(phys_addr_t paddr)
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{
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if (is_isa_arcompact()) {
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if (paddr >= ARC_UNCACHED_ADDR_SPACE)
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return true;
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} else if (paddr >= perip_base && paddr <= 0xFFFFFFFF) {
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return true;
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}
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return false;
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}
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void __iomem *ioremap(phys_addr_t paddr, unsigned long size)
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{
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phys_addr_t end;
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/* Don't allow wraparound or zero size */
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end = paddr + size - 1;
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if (!size || (end < paddr))
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return NULL;
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/*
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* If the region is h/w uncached, MMU mapping can be elided as optim
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* The cast to u32 is fine as this region can only be inside 4GB
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*/
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if (arc_uncached_addr_space(paddr))
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return (void __iomem *)(u32)paddr;
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return ioremap_prot(paddr, size, PAGE_KERNEL_NO_CACHE);
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}
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EXPORT_SYMBOL(ioremap);
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/*
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* ioremap with access flags
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* Cache semantics wise it is same as ioremap - "forced" uncached.
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* However unline vanilla ioremap which bypasses ARC MMU for addresses in
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* ARC hardware uncached region, this one still goes thru the MMU as caller
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* might need finer access control (R/W/X)
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*/
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void __iomem *ioremap_prot(phys_addr_t paddr, unsigned long size,
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unsigned long flags)
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{
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unsigned long vaddr;
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struct vm_struct *area;
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phys_addr_t off, end;
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pgprot_t prot = __pgprot(flags);
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/* Don't allow wraparound, zero size */
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end = paddr + size - 1;
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if ((!size) || (end < paddr))
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return NULL;
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/* An early platform driver might end up here */
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if (!slab_is_available())
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return NULL;
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/* force uncached */
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prot = pgprot_noncached(prot);
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/* Mappings have to be page-aligned */
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off = paddr & ~PAGE_MASK;
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paddr &= PAGE_MASK;
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size = PAGE_ALIGN(end + 1) - paddr;
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/*
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* Ok, go for it..
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*/
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area = get_vm_area(size, VM_IOREMAP);
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if (!area)
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return NULL;
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area->phys_addr = paddr;
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vaddr = (unsigned long)area->addr;
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if (ioremap_page_range(vaddr, vaddr + size, paddr, prot)) {
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vunmap((void __force *)vaddr);
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return NULL;
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}
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return (void __iomem *)(off + (char __iomem *)vaddr);
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}
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EXPORT_SYMBOL(ioremap_prot);
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void iounmap(const void __iomem *addr)
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{
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/* weird double cast to handle phys_addr_t > 32 bits */
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if (arc_uncached_addr_space((phys_addr_t)(u32)addr))
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return;
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vfree((void *)(PAGE_MASK & (unsigned long __force)addr));
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}
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EXPORT_SYMBOL(iounmap);
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