mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 17:30:59 +07:00
222 lines
7.8 KiB
C
222 lines
7.8 KiB
C
/*
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* Common Intel AGPGART and GTT definitions.
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*/
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#ifndef _INTEL_AGP_H
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#define _INTEL_AGP_H
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/* Intel registers */
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#define INTEL_APSIZE 0xb4
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#define INTEL_ATTBASE 0xb8
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#define INTEL_AGPCTRL 0xb0
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#define INTEL_NBXCFG 0x50
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#define INTEL_ERRSTS 0x91
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/* Intel i830 registers */
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#define I830_GMCH_CTRL 0x52
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#define I830_GMCH_ENABLED 0x4
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#define I830_GMCH_MEM_MASK 0x1
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#define I830_GMCH_MEM_64M 0x1
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#define I830_GMCH_MEM_128M 0
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#define I830_GMCH_GMS_MASK 0x70
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#define I830_GMCH_GMS_DISABLED 0x00
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#define I830_GMCH_GMS_LOCAL 0x10
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#define I830_GMCH_GMS_STOLEN_512 0x20
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#define I830_GMCH_GMS_STOLEN_1024 0x30
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#define I830_GMCH_GMS_STOLEN_8192 0x40
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#define I830_RDRAM_CHANNEL_TYPE 0x03010
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#define I830_RDRAM_ND(x) (((x) & 0x20) >> 5)
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#define I830_RDRAM_DDT(x) (((x) & 0x18) >> 3)
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/* This one is for I830MP w. an external graphic card */
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#define INTEL_I830_ERRSTS 0x92
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/* Intel 855GM/852GM registers */
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#define I855_GMCH_GMS_MASK 0xF0
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#define I855_GMCH_GMS_STOLEN_0M 0x0
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#define I855_GMCH_GMS_STOLEN_1M (0x1 << 4)
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#define I855_GMCH_GMS_STOLEN_4M (0x2 << 4)
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#define I855_GMCH_GMS_STOLEN_8M (0x3 << 4)
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#define I855_GMCH_GMS_STOLEN_16M (0x4 << 4)
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#define I855_GMCH_GMS_STOLEN_32M (0x5 << 4)
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#define I85X_CAPID 0x44
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#define I85X_VARIANT_MASK 0x7
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#define I85X_VARIANT_SHIFT 5
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#define I855_GME 0x0
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#define I855_GM 0x4
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#define I852_GME 0x2
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#define I852_GM 0x5
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/* Intel i845 registers */
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#define INTEL_I845_AGPM 0x51
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#define INTEL_I845_ERRSTS 0xc8
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/* Intel i860 registers */
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#define INTEL_I860_MCHCFG 0x50
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#define INTEL_I860_ERRSTS 0xc8
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/* Intel i810 registers */
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#define I810_GMADDR 0x10
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#define I810_MMADDR 0x14
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#define I810_PTE_BASE 0x10000
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#define I810_PTE_MAIN_UNCACHED 0x00000000
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#define I810_PTE_LOCAL 0x00000002
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#define I810_PTE_VALID 0x00000001
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#define I830_PTE_SYSTEM_CACHED 0x00000006
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/* GT PTE cache control fields */
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#define GEN6_PTE_UNCACHED 0x00000002
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#define GEN6_PTE_LLC 0x00000004
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#define GEN6_PTE_LLC_MLC 0x00000006
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#define GEN6_PTE_GFDT 0x00000008
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#define I810_SMRAM_MISCC 0x70
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#define I810_GFX_MEM_WIN_SIZE 0x00010000
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#define I810_GFX_MEM_WIN_32M 0x00010000
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#define I810_GMS 0x000000c0
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#define I810_GMS_DISABLE 0x00000000
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#define I810_PGETBL_CTL 0x2020
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#define I810_PGETBL_ENABLED 0x00000001
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#define I965_PGETBL_SIZE_MASK 0x0000000e
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#define I965_PGETBL_SIZE_512KB (0 << 1)
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#define I965_PGETBL_SIZE_256KB (1 << 1)
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#define I965_PGETBL_SIZE_128KB (2 << 1)
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#define I965_PGETBL_SIZE_1MB (3 << 1)
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#define I965_PGETBL_SIZE_2MB (4 << 1)
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#define I965_PGETBL_SIZE_1_5MB (5 << 1)
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#define G33_PGETBL_SIZE_MASK (3 << 8)
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#define G33_PGETBL_SIZE_1M (1 << 8)
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#define G33_PGETBL_SIZE_2M (2 << 8)
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#define I810_DRAM_CTL 0x3000
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#define I810_DRAM_ROW_0 0x00000001
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#define I810_DRAM_ROW_0_SDRAM 0x00000001
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/* Intel 815 register */
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#define INTEL_815_APCONT 0x51
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#define INTEL_815_ATTBASE_MASK ~0x1FFFFFFF
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/* Intel i820 registers */
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#define INTEL_I820_RDCR 0x51
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#define INTEL_I820_ERRSTS 0xc8
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/* Intel i840 registers */
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#define INTEL_I840_MCHCFG 0x50
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#define INTEL_I840_ERRSTS 0xc8
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/* Intel i850 registers */
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#define INTEL_I850_MCHCFG 0x50
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#define INTEL_I850_ERRSTS 0xc8
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/* intel 915G registers */
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#define I915_GMADDR 0x18
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#define I915_MMADDR 0x10
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#define I915_PTEADDR 0x1C
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#define I915_GMCH_GMS_STOLEN_48M (0x6 << 4)
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#define I915_GMCH_GMS_STOLEN_64M (0x7 << 4)
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#define G33_GMCH_GMS_STOLEN_128M (0x8 << 4)
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#define G33_GMCH_GMS_STOLEN_256M (0x9 << 4)
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#define INTEL_GMCH_GMS_STOLEN_96M (0xa << 4)
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#define INTEL_GMCH_GMS_STOLEN_160M (0xb << 4)
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#define INTEL_GMCH_GMS_STOLEN_224M (0xc << 4)
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#define INTEL_GMCH_GMS_STOLEN_352M (0xd << 4)
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#define I915_IFPADDR 0x60
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/* Intel 965G registers */
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#define I965_MSAC 0x62
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#define I965_IFPADDR 0x70
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/* Intel 7505 registers */
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#define INTEL_I7505_APSIZE 0x74
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#define INTEL_I7505_NCAPID 0x60
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#define INTEL_I7505_NISTAT 0x6c
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#define INTEL_I7505_ATTBASE 0x78
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#define INTEL_I7505_ERRSTS 0x42
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#define INTEL_I7505_AGPCTRL 0x70
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#define INTEL_I7505_MCHCFG 0x50
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#define SNB_GMCH_CTRL 0x50
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#define SNB_GMCH_GMS_STOLEN_MASK 0xF8
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#define SNB_GMCH_GMS_STOLEN_32M (1 << 3)
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#define SNB_GMCH_GMS_STOLEN_64M (2 << 3)
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#define SNB_GMCH_GMS_STOLEN_96M (3 << 3)
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#define SNB_GMCH_GMS_STOLEN_128M (4 << 3)
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#define SNB_GMCH_GMS_STOLEN_160M (5 << 3)
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#define SNB_GMCH_GMS_STOLEN_192M (6 << 3)
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#define SNB_GMCH_GMS_STOLEN_224M (7 << 3)
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#define SNB_GMCH_GMS_STOLEN_256M (8 << 3)
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#define SNB_GMCH_GMS_STOLEN_288M (9 << 3)
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#define SNB_GMCH_GMS_STOLEN_320M (0xa << 3)
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#define SNB_GMCH_GMS_STOLEN_352M (0xb << 3)
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#define SNB_GMCH_GMS_STOLEN_384M (0xc << 3)
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#define SNB_GMCH_GMS_STOLEN_416M (0xd << 3)
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#define SNB_GMCH_GMS_STOLEN_448M (0xe << 3)
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#define SNB_GMCH_GMS_STOLEN_480M (0xf << 3)
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#define SNB_GMCH_GMS_STOLEN_512M (0x10 << 3)
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#define SNB_GTT_SIZE_0M (0 << 8)
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#define SNB_GTT_SIZE_1M (1 << 8)
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#define SNB_GTT_SIZE_2M (2 << 8)
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#define SNB_GTT_SIZE_MASK (3 << 8)
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/* pci devices ids */
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#define PCI_DEVICE_ID_INTEL_E7221_HB 0x2588
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#define PCI_DEVICE_ID_INTEL_E7221_IG 0x258a
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#define PCI_DEVICE_ID_INTEL_82946GZ_HB 0x2970
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#define PCI_DEVICE_ID_INTEL_82946GZ_IG 0x2972
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#define PCI_DEVICE_ID_INTEL_82G35_HB 0x2980
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#define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982
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#define PCI_DEVICE_ID_INTEL_82965Q_HB 0x2990
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#define PCI_DEVICE_ID_INTEL_82965Q_IG 0x2992
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#define PCI_DEVICE_ID_INTEL_82965G_HB 0x29A0
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#define PCI_DEVICE_ID_INTEL_82965G_IG 0x29A2
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#define PCI_DEVICE_ID_INTEL_82965GM_HB 0x2A00
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#define PCI_DEVICE_ID_INTEL_82965GM_IG 0x2A02
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#define PCI_DEVICE_ID_INTEL_82965GME_HB 0x2A10
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#define PCI_DEVICE_ID_INTEL_82965GME_IG 0x2A12
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#define PCI_DEVICE_ID_INTEL_82945GME_HB 0x27AC
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#define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_HB 0xA010
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG 0xA011
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_HB 0xA000
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#define PCI_DEVICE_ID_INTEL_PINEVIEW_IG 0xA001
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#define PCI_DEVICE_ID_INTEL_G33_HB 0x29C0
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#define PCI_DEVICE_ID_INTEL_G33_IG 0x29C2
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#define PCI_DEVICE_ID_INTEL_Q35_HB 0x29B0
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#define PCI_DEVICE_ID_INTEL_Q35_IG 0x29B2
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#define PCI_DEVICE_ID_INTEL_Q33_HB 0x29D0
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#define PCI_DEVICE_ID_INTEL_Q33_IG 0x29D2
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#define PCI_DEVICE_ID_INTEL_B43_HB 0x2E40
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#define PCI_DEVICE_ID_INTEL_B43_IG 0x2E42
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#define PCI_DEVICE_ID_INTEL_B43_1_HB 0x2E90
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#define PCI_DEVICE_ID_INTEL_B43_1_IG 0x2E92
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#define PCI_DEVICE_ID_INTEL_GM45_HB 0x2A40
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#define PCI_DEVICE_ID_INTEL_GM45_IG 0x2A42
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_HB 0x2E00
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#define PCI_DEVICE_ID_INTEL_EAGLELAKE_IG 0x2E02
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#define PCI_DEVICE_ID_INTEL_Q45_HB 0x2E10
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#define PCI_DEVICE_ID_INTEL_Q45_IG 0x2E12
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#define PCI_DEVICE_ID_INTEL_G45_HB 0x2E20
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#define PCI_DEVICE_ID_INTEL_G45_IG 0x2E22
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#define PCI_DEVICE_ID_INTEL_G41_HB 0x2E30
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#define PCI_DEVICE_ID_INTEL_G41_IG 0x2E32
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_HB 0x0040
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG 0x0042
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_HB 0x0044
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_MA_HB 0x0062
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_MC2_HB 0x006a
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#define PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG 0x0046
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_HB 0x0100 /* Desktop */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT1_IG 0x0102
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_IG 0x0112
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_GT2_PLUS_IG 0x0122
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_HB 0x0104 /* Mobile */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT1_IG 0x0106
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_IG 0x0116
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_M_GT2_PLUS_IG 0x0126
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_HB 0x0108 /* Server */
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#define PCI_DEVICE_ID_INTEL_SANDYBRIDGE_S_IG 0x010A
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int intel_gmch_probe(struct pci_dev *pdev,
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struct agp_bridge_data *bridge);
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void intel_gmch_remove(struct pci_dev *pdev);
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#endif
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