mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-30 12:46:40 +07:00
315 lines
8.5 KiB
C
315 lines
8.5 KiB
C
/*
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* MXC GPIO support. (c) 2008 Daniel Mack <daniel@caiaq.de>
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* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
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*
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* Based on code from Freescale,
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* Copyright 2004-2006 Freescale Semiconductor, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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*/
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#include <linux/init.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/gpio.h>
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#include <mach/hardware.h>
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#include <asm-generic/bug.h>
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static struct mxc_gpio_port *mxc_gpio_ports;
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static int gpio_table_size;
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#define cpu_is_mx1_mx2() (cpu_is_mx1() || cpu_is_mx2())
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#define GPIO_DR (cpu_is_mx1_mx2() ? 0x1c : 0x00)
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#define GPIO_GDIR (cpu_is_mx1_mx2() ? 0x00 : 0x04)
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#define GPIO_PSR (cpu_is_mx1_mx2() ? 0x24 : 0x08)
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#define GPIO_ICR1 (cpu_is_mx1_mx2() ? 0x28 : 0x0C)
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#define GPIO_ICR2 (cpu_is_mx1_mx2() ? 0x2C : 0x10)
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#define GPIO_IMR (cpu_is_mx1_mx2() ? 0x30 : 0x14)
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#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
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#define GPIO_ISR (cpu_is_mx1_mx2() ? 0x34 : 0x18)
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#define GPIO_INT_LOW_LEV (cpu_is_mx1_mx2() ? 0x3 : 0x0)
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#define GPIO_INT_HIGH_LEV (cpu_is_mx1_mx2() ? 0x2 : 0x1)
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#define GPIO_INT_RISE_EDGE (cpu_is_mx1_mx2() ? 0x0 : 0x2)
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#define GPIO_INT_FALL_EDGE (cpu_is_mx1_mx2() ? 0x1 : 0x3)
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#define GPIO_INT_NONE 0x4
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/* Note: This driver assumes 32 GPIOs are handled in one register */
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static void _clear_gpio_irqstatus(struct mxc_gpio_port *port, u32 index)
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{
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__raw_writel(1 << index, port->base + GPIO_ISR);
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}
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static void _set_gpio_irqenable(struct mxc_gpio_port *port, u32 index,
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int enable)
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{
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u32 l;
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l = __raw_readl(port->base + GPIO_IMR);
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l = (l & (~(1 << index))) | (!!enable << index);
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__raw_writel(l, port->base + GPIO_IMR);
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}
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static void gpio_ack_irq(u32 irq)
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{
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u32 gpio = irq_to_gpio(irq);
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_clear_gpio_irqstatus(&mxc_gpio_ports[gpio / 32], gpio & 0x1f);
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}
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static void gpio_mask_irq(u32 irq)
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{
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u32 gpio = irq_to_gpio(irq);
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_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 0);
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}
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static void gpio_unmask_irq(u32 irq)
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{
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u32 gpio = irq_to_gpio(irq);
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_set_gpio_irqenable(&mxc_gpio_ports[gpio / 32], gpio & 0x1f, 1);
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}
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static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset);
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static int gpio_set_irq_type(u32 irq, u32 type)
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{
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u32 gpio = irq_to_gpio(irq);
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struct mxc_gpio_port *port = &mxc_gpio_ports[gpio / 32];
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u32 bit, val;
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int edge;
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void __iomem *reg = port->base;
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port->both_edges &= ~(1 << (gpio & 31));
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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edge = GPIO_INT_RISE_EDGE;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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edge = GPIO_INT_FALL_EDGE;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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val = mxc_gpio_get(&port->chip, gpio & 31);
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if (val) {
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: set GPIO %d to low trigger\n", gpio);
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} else {
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: set GPIO %d to high trigger\n", gpio);
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}
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port->both_edges |= 1 << (gpio & 31);
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break;
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case IRQ_TYPE_LEVEL_LOW:
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edge = GPIO_INT_LOW_LEV;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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edge = GPIO_INT_HIGH_LEV;
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break;
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default:
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return -EINVAL;
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}
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reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
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bit = gpio & 0xf;
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val = __raw_readl(reg) & ~(0x3 << (bit << 1));
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__raw_writel(val | (edge << (bit << 1)), reg);
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_clear_gpio_irqstatus(port, gpio & 0x1f);
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return 0;
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}
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static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio)
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{
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void __iomem *reg = port->base;
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u32 bit, val;
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int edge;
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reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */
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bit = gpio & 0xf;
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val = __raw_readl(reg);
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edge = (val >> (bit << 1)) & 3;
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val &= ~(0x3 << (bit << 1));
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switch (edge) {
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case GPIO_INT_HIGH_LEV:
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edge = GPIO_INT_LOW_LEV;
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pr_debug("mxc: switch GPIO %d to low trigger\n", gpio);
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break;
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case GPIO_INT_LOW_LEV:
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edge = GPIO_INT_HIGH_LEV;
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pr_debug("mxc: switch GPIO %d to high trigger\n", gpio);
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break;
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default:
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pr_err("mxc: invalid configuration for GPIO %d: %x\n",
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gpio, edge);
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return;
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}
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__raw_writel(val | (edge << (bit << 1)), reg);
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}
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/* handle n interrupts in one status register */
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static void mxc_gpio_irq_handler(struct mxc_gpio_port *port, u32 irq_stat)
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{
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u32 gpio_irq_no;
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gpio_irq_no = port->virtual_irq_start;
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for (; irq_stat != 0; irq_stat >>= 1, gpio_irq_no++) {
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u32 gpio = irq_to_gpio(gpio_irq_no);
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if ((irq_stat & 1) == 0)
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continue;
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BUG_ON(!(irq_desc[gpio_irq_no].handle_irq));
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if (port->both_edges & (1 << (gpio & 31)))
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mxc_flip_edge(port, gpio);
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irq_desc[gpio_irq_no].handle_irq(gpio_irq_no,
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&irq_desc[gpio_irq_no]);
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}
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}
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/* MX1 and MX3 has one interrupt *per* gpio port */
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static void mx3_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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u32 irq_stat;
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struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
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irq_stat = __raw_readl(port->base + GPIO_ISR) &
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__raw_readl(port->base + GPIO_IMR);
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mxc_gpio_irq_handler(port, irq_stat);
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}
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/* MX2 has one interrupt *for all* gpio ports */
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static void mx2_gpio_irq_handler(u32 irq, struct irq_desc *desc)
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{
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int i;
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u32 irq_msk, irq_stat;
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struct mxc_gpio_port *port = (struct mxc_gpio_port *)get_irq_data(irq);
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/* walk through all interrupt status registers */
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for (i = 0; i < gpio_table_size; i++) {
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irq_msk = __raw_readl(port[i].base + GPIO_IMR);
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if (!irq_msk)
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continue;
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irq_stat = __raw_readl(port[i].base + GPIO_ISR) & irq_msk;
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if (irq_stat)
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mxc_gpio_irq_handler(&port[i], irq_stat);
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}
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}
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static struct irq_chip gpio_irq_chip = {
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.ack = gpio_ack_irq,
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.mask = gpio_mask_irq,
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.unmask = gpio_unmask_irq,
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.set_type = gpio_set_irq_type,
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};
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static void _set_gpio_direction(struct gpio_chip *chip, unsigned offset,
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int dir)
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{
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struct mxc_gpio_port *port =
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container_of(chip, struct mxc_gpio_port, chip);
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u32 l;
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l = __raw_readl(port->base + GPIO_GDIR);
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if (dir)
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l |= 1 << offset;
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else
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l &= ~(1 << offset);
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__raw_writel(l, port->base + GPIO_GDIR);
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}
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static void mxc_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct mxc_gpio_port *port =
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container_of(chip, struct mxc_gpio_port, chip);
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void __iomem *reg = port->base + GPIO_DR;
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u32 l;
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l = (__raw_readl(reg) & (~(1 << offset))) | (value << offset);
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__raw_writel(l, reg);
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}
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static int mxc_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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struct mxc_gpio_port *port =
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container_of(chip, struct mxc_gpio_port, chip);
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return (__raw_readl(port->base + GPIO_PSR) >> offset) & 1;
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}
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static int mxc_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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_set_gpio_direction(chip, offset, 0);
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return 0;
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}
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static int mxc_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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mxc_gpio_set(chip, offset, value);
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_set_gpio_direction(chip, offset, 1);
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return 0;
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}
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int __init mxc_gpio_init(struct mxc_gpio_port *port, int cnt)
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{
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int i, j;
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/* save for local usage */
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mxc_gpio_ports = port;
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gpio_table_size = cnt;
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printk(KERN_INFO "MXC GPIO hardware\n");
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for (i = 0; i < cnt; i++) {
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/* disable the interrupt and clear the status */
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__raw_writel(0, port[i].base + GPIO_IMR);
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__raw_writel(~0, port[i].base + GPIO_ISR);
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for (j = port[i].virtual_irq_start;
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j < port[i].virtual_irq_start + 32; j++) {
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set_irq_chip(j, &gpio_irq_chip);
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set_irq_handler(j, handle_edge_irq);
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set_irq_flags(j, IRQF_VALID);
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}
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/* register gpio chip */
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port[i].chip.direction_input = mxc_gpio_direction_input;
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port[i].chip.direction_output = mxc_gpio_direction_output;
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port[i].chip.get = mxc_gpio_get;
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port[i].chip.set = mxc_gpio_set;
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port[i].chip.base = i * 32;
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port[i].chip.ngpio = 32;
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/* its a serious configuration bug when it fails */
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BUG_ON( gpiochip_add(&port[i].chip) < 0 );
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if (cpu_is_mx1() || cpu_is_mx3() || cpu_is_mx25()) {
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/* setup one handler for each entry */
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set_irq_chained_handler(port[i].irq, mx3_gpio_irq_handler);
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set_irq_data(port[i].irq, &port[i]);
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}
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}
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if (cpu_is_mx2()) {
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/* setup one handler for all GPIO interrupts */
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set_irq_chained_handler(port[0].irq, mx2_gpio_irq_handler);
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set_irq_data(port[0].irq, port);
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}
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return 0;
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}
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