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69501078fc
Add PCIe Host (RC) and Endpoint (EP) device tree schema for Cadence PCIe core library. Platforms using Cadence PCIe core can include the schemas added here in the platform specific schemas. Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Rob Herring <robh@kernel.org>
28 lines
684 B
YAML
28 lines
684 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/pci/cdns-pcie-host.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: Cadence PCIe Host
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maintainers:
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- Tom Joseph <tjoseph@cadence.com>
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allOf:
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- $ref: "/schemas/pci/pci-bus.yaml#"
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- $ref: "cdns-pcie.yaml#"
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properties:
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cdns,no-bar-match-nbits:
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description:
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Set into the no BAR match register to configure the number of least
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significant bits kept during inbound (PCIe -> AXI) address translations
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allOf:
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- $ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 64
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default: 32
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msi-parent: true
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