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e482c01dc7
One irqsteer channel can support up to 8 output interrupts. Cc: Rob Herring <robh+dt@kernel.org> Cc: Shawn Guo <shawnguo@kernel.org> Cc: devicetree@vger.kernel.org Reviewed-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
36 lines
1.2 KiB
Plaintext
36 lines
1.2 KiB
Plaintext
Freescale IRQSTEER Interrupt multiplexer
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Required properties:
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- compatible: should be:
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- "fsl,imx8m-irqsteer"
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- "fsl,imx-irqsteer"
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- reg: Physical base address and size of registers.
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- interrupts: Should contain the up to 8 parent interrupt lines used to
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multiplex the input interrupts. They should be specified sequentially
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from output 0 to 7.
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- clocks: Should contain one clock for entry in clock-names
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see Documentation/devicetree/bindings/clock/clock-bindings.txt
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- clock-names:
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- "ipg": main logic clock
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- interrupt-controller: Identifies the node as an interrupt controller.
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- #interrupt-cells: Specifies the number of cells needed to encode an
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interrupt source. The value must be 1.
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- fsl,channel: The output channel that all input IRQs should be steered into.
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- fsl,num-irqs: Number of input interrupts of this channel.
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Should be multiple of 32 input interrupts and up to 512 interrupts.
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Example:
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interrupt-controller@32e2d000 {
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compatible = "fsl,imx8m-irqsteer", "fsl,imx-irqsteer";
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reg = <0x32e2d000 0x1000>;
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interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>;
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clock-names = "ipg";
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fsl,channel = <0>;
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fsl,num-irqs = <64>;
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interrupt-controller;
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#interrupt-cells = <1>;
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};
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