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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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2dc10ad81f
- "genirq: Introduce generic irq migration for cpu hotunplugged" patch merged from tip/irq/for-arm to allow the arm64-specific part to be upstreamed via the arm64 tree - CPU feature detection reworked to cope with heterogeneous systems where CPUs may not have exactly the same features. The features reported by the kernel via internal data structures or ELF_HWCAP are delayed until all the CPUs are up (and before user space starts) - Support for 16KB pages, with the additional bonus of a 36-bit VA space, though the latter only depending on EXPERT - Implement native {relaxed, acquire, release} atomics for arm64 - New ASID allocation algorithm which avoids IPI on roll-over, together with TLB invalidation optimisations (using local vs global where feasible) - KASan support for arm64 - EFI_STUB clean-up and isolation for the kernel proper (required by KASan) - copy_{to,from,in}_user optimisations (sharing the memcpy template) - perf: moving arm64 to the arm32/64 shared PMU framework - L1_CACHE_BYTES increased to 128 to accommodate Cavium hardware - Support for the contiguous PTE hint on kernel mapping (16 consecutive entries may be able to use a single TLB entry) - Generic CONFIG_HZ now used on arm64 - defconfig updates -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWOkmIAAoJEGvWsS0AyF7x4GgQAINU3NePjFFvWZNCkqobeH9+ jFKwtXamIudhTSdnXNXyYWmtRL9Krg3qI4zDQf68dvDFAZAze2kVuOi1yPpCbpFZ /j/afNyQc7+PoyqRAzmT+EMPZlcuOA84Prrl1r3QWZ58QaFeVk/6ZxrHunTHxN0x mR9PIXfWx73MTo+UnG8FChkmEY6LmV4XpemgTaMR9FqFhdT51OZSxDDAYXOTm4JW a5HdN9OWjjJ2rhLlFEaC7tszG9B5doHdy2tr5ge/YERVJzIPDogHkMe8ZhfAJc+x SQU5tKN6Pg4MOi+dLhxlk0/mKCvHLiEQ5KVREJnt8GxupAR54Bat+DQ+rP9cSnpq dRQTcARIOyy9LGgy+ROAsSo+NiyM5WuJ0/WJUYKmgWTJOfczRYoZv6TMKlwNOUYb tGLCZHhKPM3yBHJlWbQykl3xmSuudxCMmjlZzg7B+MVfTP6uo0CRSPmYl+v67q+J bBw/Z2RYXWYGnvlc6OfbMeImI6prXeE36+5ytyJFga0m+IqcTzRGzjcLxKEvdbiU pr8n9i+hV9iSsT/UwukXZ8ay6zH7PrTLzILWQlieutfXlvha7MYeGxnkbLmdYcfe GCj374io5cdImHcVKmfhnOMlFOLuOHphl9cmsd/O2LmCIqBj9BIeNH2Om8mHVK2F YHczMdpESlJApE7kUc1e =3six -----END PGP SIGNATURE----- Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: - "genirq: Introduce generic irq migration for cpu hotunplugged" patch merged from tip/irq/for-arm to allow the arm64-specific part to be upstreamed via the arm64 tree - CPU feature detection reworked to cope with heterogeneous systems where CPUs may not have exactly the same features. The features reported by the kernel via internal data structures or ELF_HWCAP are delayed until all the CPUs are up (and before user space starts) - Support for 16KB pages, with the additional bonus of a 36-bit VA space, though the latter only depending on EXPERT - Implement native {relaxed, acquire, release} atomics for arm64 - New ASID allocation algorithm which avoids IPI on roll-over, together with TLB invalidation optimisations (using local vs global where feasible) - KASan support for arm64 - EFI_STUB clean-up and isolation for the kernel proper (required by KASan) - copy_{to,from,in}_user optimisations (sharing the memcpy template) - perf: moving arm64 to the arm32/64 shared PMU framework - L1_CACHE_BYTES increased to 128 to accommodate Cavium hardware - Support for the contiguous PTE hint on kernel mapping (16 consecutive entries may be able to use a single TLB entry) - Generic CONFIG_HZ now used on arm64 - defconfig updates * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (91 commits) arm64/efi: fix libstub build under CONFIG_MODVERSIONS ARM64: Enable multi-core scheduler support by default arm64/efi: move arm64 specific stub C code to libstub arm64: page-align sections for DEBUG_RODATA arm64: Fix build with CONFIG_ZONE_DMA=n arm64: Fix compat register mappings arm64: Increase the max granular size arm64: remove bogus TASK_SIZE_64 check arm64: make Timer Interrupt Frequency selectable arm64/mm: use PAGE_ALIGNED instead of IS_ALIGNED arm64: cachetype: fix definitions of ICACHEF_* flags arm64: cpufeature: declare enable_cpu_capabilities as static genirq: Make the cpuhotplug migration code less noisy arm64: Constify hwcap name string arrays arm64/kvm: Make use of the system wide safe values arm64/debug: Make use of the system wide safe value arm64: Move FP/ASIMD hwcap handling to common code arm64/HWCAP: Use system wide safe values arm64/capabilities: Make use of system wide safe value arm64: Delay cpu feature capability checks ...
151 lines
5.7 KiB
C
151 lines
5.7 KiB
C
/*
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* Based on arch/arm/include/asm/atomic.h
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*
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* Copyright (C) 1996 Russell King.
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* Copyright (C) 2002 Deep Blue Solutions Ltd.
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* Copyright (C) 2012 ARM Ltd.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __ASM_ATOMIC_H
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#define __ASM_ATOMIC_H
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include <asm/barrier.h>
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#include <asm/lse.h>
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#ifdef __KERNEL__
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#define __ARM64_IN_ATOMIC_IMPL
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#if defined(CONFIG_ARM64_LSE_ATOMICS) && defined(CONFIG_AS_LSE)
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#include <asm/atomic_lse.h>
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#else
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#include <asm/atomic_ll_sc.h>
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#endif
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#undef __ARM64_IN_ATOMIC_IMPL
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#include <asm/cmpxchg.h>
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#define ___atomic_add_unless(v, a, u, sfx) \
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({ \
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typeof((v)->counter) c, old; \
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\
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c = atomic##sfx##_read(v); \
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while (c != (u) && \
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(old = atomic##sfx##_cmpxchg((v), c, c + (a))) != c) \
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c = old; \
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c; \
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})
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#define ATOMIC_INIT(i) { (i) }
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#define atomic_read(v) READ_ONCE((v)->counter)
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#define atomic_set(v, i) WRITE_ONCE(((v)->counter), (i))
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#define atomic_add_return_relaxed atomic_add_return_relaxed
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#define atomic_add_return_acquire atomic_add_return_acquire
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#define atomic_add_return_release atomic_add_return_release
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#define atomic_add_return atomic_add_return
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#define atomic_inc_return_relaxed(v) atomic_add_return_relaxed(1, (v))
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#define atomic_inc_return_acquire(v) atomic_add_return_acquire(1, (v))
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#define atomic_inc_return_release(v) atomic_add_return_release(1, (v))
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#define atomic_inc_return(v) atomic_add_return(1, (v))
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#define atomic_sub_return_relaxed atomic_sub_return_relaxed
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#define atomic_sub_return_acquire atomic_sub_return_acquire
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#define atomic_sub_return_release atomic_sub_return_release
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#define atomic_sub_return atomic_sub_return
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#define atomic_dec_return_relaxed(v) atomic_sub_return_relaxed(1, (v))
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#define atomic_dec_return_acquire(v) atomic_sub_return_acquire(1, (v))
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#define atomic_dec_return_release(v) atomic_sub_return_release(1, (v))
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#define atomic_dec_return(v) atomic_sub_return(1, (v))
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#define atomic_xchg_relaxed(v, new) xchg_relaxed(&((v)->counter), (new))
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#define atomic_xchg_acquire(v, new) xchg_acquire(&((v)->counter), (new))
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#define atomic_xchg_release(v, new) xchg_release(&((v)->counter), (new))
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#define atomic_xchg(v, new) xchg(&((v)->counter), (new))
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#define atomic_cmpxchg_relaxed(v, old, new) \
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cmpxchg_relaxed(&((v)->counter), (old), (new))
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#define atomic_cmpxchg_acquire(v, old, new) \
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cmpxchg_acquire(&((v)->counter), (old), (new))
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#define atomic_cmpxchg_release(v, old, new) \
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cmpxchg_release(&((v)->counter), (old), (new))
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#define atomic_cmpxchg(v, old, new) cmpxchg(&((v)->counter), (old), (new))
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#define atomic_inc(v) atomic_add(1, (v))
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#define atomic_dec(v) atomic_sub(1, (v))
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#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
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#define atomic_dec_and_test(v) (atomic_dec_return(v) == 0)
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#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
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#define atomic_add_negative(i, v) (atomic_add_return((i), (v)) < 0)
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#define __atomic_add_unless(v, a, u) ___atomic_add_unless(v, a, u,)
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#define atomic_andnot atomic_andnot
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/*
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* 64-bit atomic operations.
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*/
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#define ATOMIC64_INIT ATOMIC_INIT
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#define atomic64_read atomic_read
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#define atomic64_set atomic_set
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#define atomic64_add_return_relaxed atomic64_add_return_relaxed
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#define atomic64_add_return_acquire atomic64_add_return_acquire
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#define atomic64_add_return_release atomic64_add_return_release
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#define atomic64_add_return atomic64_add_return
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#define atomic64_inc_return_relaxed(v) atomic64_add_return_relaxed(1, (v))
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#define atomic64_inc_return_acquire(v) atomic64_add_return_acquire(1, (v))
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#define atomic64_inc_return_release(v) atomic64_add_return_release(1, (v))
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#define atomic64_inc_return(v) atomic64_add_return(1, (v))
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#define atomic64_sub_return_relaxed atomic64_sub_return_relaxed
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#define atomic64_sub_return_acquire atomic64_sub_return_acquire
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#define atomic64_sub_return_release atomic64_sub_return_release
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#define atomic64_sub_return atomic64_sub_return
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#define atomic64_dec_return_relaxed(v) atomic64_sub_return_relaxed(1, (v))
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#define atomic64_dec_return_acquire(v) atomic64_sub_return_acquire(1, (v))
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#define atomic64_dec_return_release(v) atomic64_sub_return_release(1, (v))
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#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
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#define atomic64_xchg_relaxed atomic_xchg_relaxed
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#define atomic64_xchg_acquire atomic_xchg_acquire
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#define atomic64_xchg_release atomic_xchg_release
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#define atomic64_xchg atomic_xchg
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#define atomic64_cmpxchg_relaxed atomic_cmpxchg_relaxed
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#define atomic64_cmpxchg_acquire atomic_cmpxchg_acquire
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#define atomic64_cmpxchg_release atomic_cmpxchg_release
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#define atomic64_cmpxchg atomic_cmpxchg
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#define atomic64_inc(v) atomic64_add(1, (v))
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#define atomic64_dec(v) atomic64_sub(1, (v))
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#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
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#define atomic64_dec_and_test(v) (atomic64_dec_return(v) == 0)
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#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
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#define atomic64_add_negative(i, v) (atomic64_add_return((i), (v)) < 0)
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#define atomic64_add_unless(v, a, u) (___atomic_add_unless(v, a, u, 64) != u)
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#define atomic64_andnot atomic64_andnot
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#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
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#endif
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#endif
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