linux_dsm_epyc7002/arch/riscv/include
Palmer Dabbelt 18856604b3 RISC-V: Clear load reservations while restoring hart contexts
This is almost entirely a comment.  The bug is unlikely to manifest on
existing hardware because there is a timeout on load reservations, but
manifests on QEMU because there is no timeout.

Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Reviewed-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>
2019-10-01 13:16:40 -07:00
..
asm RISC-V: Clear load reservations while restoring hart contexts 2019-10-01 13:16:40 -07:00
uapi/asm riscv: Add support for perf registers sampling 2019-09-05 00:48:58 -07:00