mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 01:05:37 +07:00
36d527dead
We always skipped flushing the BLT ring if the request flush did not include the RENDER domain. However, this neglects that we try to flush the COMMAND domain after every batch and before the breadcrumb interrupt (to make sure the batch is indeed completed prior to the interrupt firing and so insuring CPU coherency). As a result of the missing flush, incoherency did indeed creep in, most notable when using lots of command buffers and so potentially rewritting an active command buffer (i.e. the GPU was still executing from it even though the following interrupt had already fired and the request/buffer retired). As all ring->flush routines now have the same preconditions, de-duplicate and move those checks up into i915_gem_flush_ring(). Fixes gem_linear_blit. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=35284 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch> Tested-by: mengmeng.meng@intel.com
1353 lines
32 KiB
C
1353 lines
32 KiB
C
/*
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* Copyright © 2008-2010 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Zou Nan hai <nanhai.zou@intel.com>
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* Xiang Hai hao<haihao.xiang@intel.com>
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "i915_drv.h"
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#include "i915_drm.h"
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#include "i915_trace.h"
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#include "intel_drv.h"
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static inline int ring_space(struct intel_ring_buffer *ring)
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{
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int space = (ring->head & HEAD_ADDR) - (ring->tail + 8);
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if (space < 0)
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space += ring->size;
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return space;
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}
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static u32 i915_gem_get_seqno(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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u32 seqno;
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seqno = dev_priv->next_seqno;
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/* reserve 0 for non-seqno */
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if (++dev_priv->next_seqno == 0)
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dev_priv->next_seqno = 1;
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return seqno;
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}
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static int
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render_ring_flush(struct intel_ring_buffer *ring,
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u32 invalidate_domains,
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u32 flush_domains)
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{
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struct drm_device *dev = ring->dev;
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u32 cmd;
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int ret;
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/*
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* read/write caches:
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*
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* I915_GEM_DOMAIN_RENDER is always invalidated, but is
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* only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is
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* also flushed at 2d versus 3d pipeline switches.
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*
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* read-only caches:
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*
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* I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
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* MI_READ_FLUSH is set, and is always flushed on 965.
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*
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* I915_GEM_DOMAIN_COMMAND may not exist?
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*
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* I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
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* invalidated when MI_EXE_FLUSH is set.
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*
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* I915_GEM_DOMAIN_VERTEX, which exists on 965, is
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* invalidated with every MI_FLUSH.
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*
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* TLBs:
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*
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* On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
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* and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
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* I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
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* are flushed at any MI_FLUSH.
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*/
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cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
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if ((invalidate_domains|flush_domains) &
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I915_GEM_DOMAIN_RENDER)
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cmd &= ~MI_NO_WRITE_FLUSH;
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if (INTEL_INFO(dev)->gen < 4) {
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/*
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* On the 965, the sampler cache always gets flushed
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* and this bit is reserved.
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*/
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if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
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cmd |= MI_READ_FLUSH;
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}
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if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
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cmd |= MI_EXE_FLUSH;
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if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
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(IS_G4X(dev) || IS_GEN5(dev)))
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cmd |= MI_INVALIDATE_ISP;
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ret = intel_ring_begin(ring, 2);
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if (ret)
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return ret;
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intel_ring_emit(ring, cmd);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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return 0;
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}
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static void ring_write_tail(struct intel_ring_buffer *ring,
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u32 value)
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{
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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I915_WRITE_TAIL(ring, value);
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}
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u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
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{
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
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RING_ACTHD(ring->mmio_base) : ACTHD;
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return I915_READ(acthd_reg);
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}
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static int init_ring_common(struct intel_ring_buffer *ring)
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{
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drm_i915_private_t *dev_priv = ring->dev->dev_private;
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struct drm_i915_gem_object *obj = ring->obj;
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u32 head;
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/* Stop the ring if it's running. */
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I915_WRITE_CTL(ring, 0);
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I915_WRITE_HEAD(ring, 0);
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ring->write_tail(ring, 0);
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/* Initialize the ring. */
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I915_WRITE_START(ring, obj->gtt_offset);
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head = I915_READ_HEAD(ring) & HEAD_ADDR;
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/* G45 ring initialization fails to reset head to zero */
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if (head != 0) {
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DRM_DEBUG_KMS("%s head not reset to zero "
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"ctl %08x head %08x tail %08x start %08x\n",
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ring->name,
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I915_READ_CTL(ring),
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I915_READ_HEAD(ring),
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I915_READ_TAIL(ring),
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I915_READ_START(ring));
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I915_WRITE_HEAD(ring, 0);
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if (I915_READ_HEAD(ring) & HEAD_ADDR) {
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DRM_ERROR("failed to set %s head to zero "
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"ctl %08x head %08x tail %08x start %08x\n",
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ring->name,
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I915_READ_CTL(ring),
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I915_READ_HEAD(ring),
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I915_READ_TAIL(ring),
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I915_READ_START(ring));
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}
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}
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I915_WRITE_CTL(ring,
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((ring->size - PAGE_SIZE) & RING_NR_PAGES)
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| RING_REPORT_64K | RING_VALID);
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/* If the head is still not zero, the ring is dead */
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if ((I915_READ_CTL(ring) & RING_VALID) == 0 ||
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I915_READ_START(ring) != obj->gtt_offset ||
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(I915_READ_HEAD(ring) & HEAD_ADDR) != 0) {
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DRM_ERROR("%s initialization failed "
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"ctl %08x head %08x tail %08x start %08x\n",
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ring->name,
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I915_READ_CTL(ring),
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I915_READ_HEAD(ring),
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I915_READ_TAIL(ring),
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I915_READ_START(ring));
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return -EIO;
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}
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if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
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i915_kernel_lost_context(ring->dev);
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else {
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ring->head = I915_READ_HEAD(ring);
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ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
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ring->space = ring_space(ring);
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}
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return 0;
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}
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/*
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* 965+ support PIPE_CONTROL commands, which provide finer grained control
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* over cache flushing.
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*/
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struct pipe_control {
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struct drm_i915_gem_object *obj;
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volatile u32 *cpu_page;
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u32 gtt_offset;
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};
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static int
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init_pipe_control(struct intel_ring_buffer *ring)
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{
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struct pipe_control *pc;
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struct drm_i915_gem_object *obj;
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int ret;
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if (ring->private)
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return 0;
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pc = kmalloc(sizeof(*pc), GFP_KERNEL);
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if (!pc)
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return -ENOMEM;
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obj = i915_gem_alloc_object(ring->dev, 4096);
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if (obj == NULL) {
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DRM_ERROR("Failed to allocate seqno page\n");
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ret = -ENOMEM;
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goto err;
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}
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obj->agp_type = AGP_USER_CACHED_MEMORY;
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ret = i915_gem_object_pin(obj, 4096, true);
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if (ret)
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goto err_unref;
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pc->gtt_offset = obj->gtt_offset;
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pc->cpu_page = kmap(obj->pages[0]);
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if (pc->cpu_page == NULL)
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goto err_unpin;
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pc->obj = obj;
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ring->private = pc;
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return 0;
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err_unpin:
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i915_gem_object_unpin(obj);
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err_unref:
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drm_gem_object_unreference(&obj->base);
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err:
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kfree(pc);
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return ret;
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}
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static void
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cleanup_pipe_control(struct intel_ring_buffer *ring)
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{
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struct pipe_control *pc = ring->private;
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struct drm_i915_gem_object *obj;
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if (!ring->private)
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return;
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obj = pc->obj;
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kunmap(obj->pages[0]);
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i915_gem_object_unpin(obj);
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drm_gem_object_unreference(&obj->base);
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kfree(pc);
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ring->private = NULL;
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}
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static int init_render_ring(struct intel_ring_buffer *ring)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret = init_ring_common(ring);
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if (INTEL_INFO(dev)->gen > 3) {
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int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH;
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if (IS_GEN6(dev))
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mode |= MI_FLUSH_ENABLE << 16 | MI_FLUSH_ENABLE;
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I915_WRITE(MI_MODE, mode);
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}
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if (INTEL_INFO(dev)->gen >= 6) {
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} else if (IS_GEN5(dev)) {
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ret = init_pipe_control(ring);
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if (ret)
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return ret;
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}
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return ret;
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}
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static void render_ring_cleanup(struct intel_ring_buffer *ring)
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{
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if (!ring->private)
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return;
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cleanup_pipe_control(ring);
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}
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static void
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update_semaphore(struct intel_ring_buffer *ring, int i, u32 seqno)
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{
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struct drm_device *dev = ring->dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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int id;
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/*
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* cs -> 1 = vcs, 0 = bcs
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* vcs -> 1 = bcs, 0 = cs,
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* bcs -> 1 = cs, 0 = vcs.
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*/
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id = ring - dev_priv->ring;
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id += 2 - i;
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id %= 3;
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intel_ring_emit(ring,
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MI_SEMAPHORE_MBOX |
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MI_SEMAPHORE_REGISTER |
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MI_SEMAPHORE_UPDATE);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring,
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RING_SYNC_0(dev_priv->ring[id].mmio_base) + 4*i);
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}
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static int
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gen6_add_request(struct intel_ring_buffer *ring,
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u32 *result)
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{
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u32 seqno;
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int ret;
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ret = intel_ring_begin(ring, 10);
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if (ret)
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return ret;
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seqno = i915_gem_get_seqno(ring->dev);
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update_semaphore(ring, 0, seqno);
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update_semaphore(ring, 1, seqno);
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intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
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intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, MI_USER_INTERRUPT);
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intel_ring_advance(ring);
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*result = seqno;
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return 0;
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}
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int
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intel_ring_sync(struct intel_ring_buffer *ring,
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struct intel_ring_buffer *to,
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u32 seqno)
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{
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int ret;
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ret = intel_ring_begin(ring, 4);
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if (ret)
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return ret;
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intel_ring_emit(ring,
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MI_SEMAPHORE_MBOX |
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MI_SEMAPHORE_REGISTER |
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intel_ring_sync_index(ring, to) << 17 |
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MI_SEMAPHORE_COMPARE);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, 0);
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intel_ring_emit(ring, MI_NOOP);
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intel_ring_advance(ring);
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return 0;
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}
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#define PIPE_CONTROL_FLUSH(ring__, addr__) \
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do { \
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intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE | \
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PIPE_CONTROL_DEPTH_STALL | 2); \
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intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \
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intel_ring_emit(ring__, 0); \
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intel_ring_emit(ring__, 0); \
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} while (0)
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static int
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pc_render_add_request(struct intel_ring_buffer *ring,
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u32 *result)
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{
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struct drm_device *dev = ring->dev;
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u32 seqno = i915_gem_get_seqno(dev);
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struct pipe_control *pc = ring->private;
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u32 scratch_addr = pc->gtt_offset + 128;
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int ret;
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|
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/* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
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* incoherent with writes to memory, i.e. completely fubar,
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* so we need to use PIPE_NOTIFY instead.
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*
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* However, we also need to workaround the qword write
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* incoherence by flushing the 6 PIPE_NOTIFY buffers out to
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* memory before requesting an interrupt.
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*/
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ret = intel_ring_begin(ring, 32);
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if (ret)
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return ret;
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|
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intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH);
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intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
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intel_ring_emit(ring, seqno);
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intel_ring_emit(ring, 0);
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128; /* write to separate cachelines */
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
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scratch_addr += 128;
|
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PIPE_CONTROL_FLUSH(ring, scratch_addr);
|
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intel_ring_emit(ring, GFX_OP_PIPE_CONTROL | PIPE_CONTROL_QW_WRITE |
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PIPE_CONTROL_WC_FLUSH | PIPE_CONTROL_TC_FLUSH |
|
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PIPE_CONTROL_NOTIFY);
|
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intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
|
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intel_ring_emit(ring, seqno);
|
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intel_ring_emit(ring, 0);
|
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intel_ring_advance(ring);
|
|
|
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*result = seqno;
|
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return 0;
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}
|
|
|
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static int
|
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render_ring_add_request(struct intel_ring_buffer *ring,
|
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u32 *result)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
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u32 seqno = i915_gem_get_seqno(dev);
|
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int ret;
|
|
|
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ret = intel_ring_begin(ring, 4);
|
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if (ret)
|
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return ret;
|
|
|
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intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
|
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intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
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intel_ring_emit(ring, seqno);
|
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intel_ring_emit(ring, MI_USER_INTERRUPT);
|
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intel_ring_advance(ring);
|
|
|
|
*result = seqno;
|
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return 0;
|
|
}
|
|
|
|
static u32
|
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ring_get_seqno(struct intel_ring_buffer *ring)
|
|
{
|
|
return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
|
|
}
|
|
|
|
static u32
|
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pc_render_get_seqno(struct intel_ring_buffer *ring)
|
|
{
|
|
struct pipe_control *pc = ring->private;
|
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return pc->cpu_page[0];
|
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}
|
|
|
|
static void
|
|
ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
|
|
{
|
|
dev_priv->gt_irq_mask &= ~mask;
|
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I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
|
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POSTING_READ(GTIMR);
|
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}
|
|
|
|
static void
|
|
ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
|
|
{
|
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dev_priv->gt_irq_mask |= mask;
|
|
I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
|
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POSTING_READ(GTIMR);
|
|
}
|
|
|
|
static void
|
|
i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask)
|
|
{
|
|
dev_priv->irq_mask &= ~mask;
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
POSTING_READ(IMR);
|
|
}
|
|
|
|
static void
|
|
i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask)
|
|
{
|
|
dev_priv->irq_mask |= mask;
|
|
I915_WRITE(IMR, dev_priv->irq_mask);
|
|
POSTING_READ(IMR);
|
|
}
|
|
|
|
static bool
|
|
render_ring_get_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
if (!dev->irq_enabled)
|
|
return false;
|
|
|
|
spin_lock(&ring->irq_lock);
|
|
if (ring->irq_refcount++ == 0) {
|
|
if (HAS_PCH_SPLIT(dev))
|
|
ironlake_enable_irq(dev_priv,
|
|
GT_PIPE_NOTIFY | GT_USER_INTERRUPT);
|
|
else
|
|
i915_enable_irq(dev_priv, I915_USER_INTERRUPT);
|
|
}
|
|
spin_unlock(&ring->irq_lock);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void
|
|
render_ring_put_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
spin_lock(&ring->irq_lock);
|
|
if (--ring->irq_refcount == 0) {
|
|
if (HAS_PCH_SPLIT(dev))
|
|
ironlake_disable_irq(dev_priv,
|
|
GT_USER_INTERRUPT |
|
|
GT_PIPE_NOTIFY);
|
|
else
|
|
i915_disable_irq(dev_priv, I915_USER_INTERRUPT);
|
|
}
|
|
spin_unlock(&ring->irq_lock);
|
|
}
|
|
|
|
void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
|
|
{
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
|
u32 mmio = IS_GEN6(ring->dev) ?
|
|
RING_HWS_PGA_GEN6(ring->mmio_base) :
|
|
RING_HWS_PGA(ring->mmio_base);
|
|
I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
|
|
POSTING_READ(mmio);
|
|
}
|
|
|
|
static int
|
|
bsd_ring_flush(struct intel_ring_buffer *ring,
|
|
u32 invalidate_domains,
|
|
u32 flush_domains)
|
|
{
|
|
int ret;
|
|
|
|
ret = intel_ring_begin(ring, 2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_ring_emit(ring, MI_FLUSH);
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
intel_ring_advance(ring);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
ring_add_request(struct intel_ring_buffer *ring,
|
|
u32 *result)
|
|
{
|
|
u32 seqno;
|
|
int ret;
|
|
|
|
ret = intel_ring_begin(ring, 4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
seqno = i915_gem_get_seqno(ring->dev);
|
|
|
|
intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
|
|
intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
intel_ring_emit(ring, seqno);
|
|
intel_ring_emit(ring, MI_USER_INTERRUPT);
|
|
intel_ring_advance(ring);
|
|
|
|
*result = seqno;
|
|
return 0;
|
|
}
|
|
|
|
static bool
|
|
ring_get_irq(struct intel_ring_buffer *ring, u32 flag)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
if (!dev->irq_enabled)
|
|
return false;
|
|
|
|
spin_lock(&ring->irq_lock);
|
|
if (ring->irq_refcount++ == 0)
|
|
ironlake_enable_irq(dev_priv, flag);
|
|
spin_unlock(&ring->irq_lock);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void
|
|
ring_put_irq(struct intel_ring_buffer *ring, u32 flag)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
spin_lock(&ring->irq_lock);
|
|
if (--ring->irq_refcount == 0)
|
|
ironlake_disable_irq(dev_priv, flag);
|
|
spin_unlock(&ring->irq_lock);
|
|
}
|
|
|
|
static bool
|
|
gen6_ring_get_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
if (!dev->irq_enabled)
|
|
return false;
|
|
|
|
spin_lock(&ring->irq_lock);
|
|
if (ring->irq_refcount++ == 0) {
|
|
ring->irq_mask &= ~rflag;
|
|
I915_WRITE_IMR(ring, ring->irq_mask);
|
|
ironlake_enable_irq(dev_priv, gflag);
|
|
}
|
|
spin_unlock(&ring->irq_lock);
|
|
|
|
return true;
|
|
}
|
|
|
|
static void
|
|
gen6_ring_put_irq(struct intel_ring_buffer *ring, u32 gflag, u32 rflag)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
spin_lock(&ring->irq_lock);
|
|
if (--ring->irq_refcount == 0) {
|
|
ring->irq_mask |= rflag;
|
|
I915_WRITE_IMR(ring, ring->irq_mask);
|
|
ironlake_disable_irq(dev_priv, gflag);
|
|
}
|
|
spin_unlock(&ring->irq_lock);
|
|
}
|
|
|
|
static bool
|
|
bsd_ring_get_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
return ring_get_irq(ring, GT_BSD_USER_INTERRUPT);
|
|
}
|
|
static void
|
|
bsd_ring_put_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
ring_put_irq(ring, GT_BSD_USER_INTERRUPT);
|
|
}
|
|
|
|
static int
|
|
ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length)
|
|
{
|
|
int ret;
|
|
|
|
ret = intel_ring_begin(ring, 2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_ring_emit(ring,
|
|
MI_BATCH_BUFFER_START | (2 << 6) |
|
|
MI_BATCH_NON_SECURE_I965);
|
|
intel_ring_emit(ring, offset);
|
|
intel_ring_advance(ring);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
|
|
u32 offset, u32 len)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
int ret;
|
|
|
|
if (IS_I830(dev) || IS_845G(dev)) {
|
|
ret = intel_ring_begin(ring, 4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_ring_emit(ring, MI_BATCH_BUFFER);
|
|
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
|
|
intel_ring_emit(ring, offset + len - 8);
|
|
intel_ring_emit(ring, 0);
|
|
} else {
|
|
ret = intel_ring_begin(ring, 2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
intel_ring_emit(ring,
|
|
MI_BATCH_BUFFER_START | (2 << 6) |
|
|
MI_BATCH_NON_SECURE_I965);
|
|
intel_ring_emit(ring, offset);
|
|
} else {
|
|
intel_ring_emit(ring,
|
|
MI_BATCH_BUFFER_START | (2 << 6));
|
|
intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE);
|
|
}
|
|
}
|
|
intel_ring_advance(ring);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void cleanup_status_page(struct intel_ring_buffer *ring)
|
|
{
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
|
struct drm_i915_gem_object *obj;
|
|
|
|
obj = ring->status_page.obj;
|
|
if (obj == NULL)
|
|
return;
|
|
|
|
kunmap(obj->pages[0]);
|
|
i915_gem_object_unpin(obj);
|
|
drm_gem_object_unreference(&obj->base);
|
|
ring->status_page.obj = NULL;
|
|
|
|
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
|
}
|
|
|
|
static int init_status_page(struct intel_ring_buffer *ring)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct drm_i915_gem_object *obj;
|
|
int ret;
|
|
|
|
obj = i915_gem_alloc_object(dev, 4096);
|
|
if (obj == NULL) {
|
|
DRM_ERROR("Failed to allocate status page\n");
|
|
ret = -ENOMEM;
|
|
goto err;
|
|
}
|
|
obj->agp_type = AGP_USER_CACHED_MEMORY;
|
|
|
|
ret = i915_gem_object_pin(obj, 4096, true);
|
|
if (ret != 0) {
|
|
goto err_unref;
|
|
}
|
|
|
|
ring->status_page.gfx_addr = obj->gtt_offset;
|
|
ring->status_page.page_addr = kmap(obj->pages[0]);
|
|
if (ring->status_page.page_addr == NULL) {
|
|
memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map));
|
|
goto err_unpin;
|
|
}
|
|
ring->status_page.obj = obj;
|
|
memset(ring->status_page.page_addr, 0, PAGE_SIZE);
|
|
|
|
intel_ring_setup_status_page(ring);
|
|
DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
|
|
ring->name, ring->status_page.gfx_addr);
|
|
|
|
return 0;
|
|
|
|
err_unpin:
|
|
i915_gem_object_unpin(obj);
|
|
err_unref:
|
|
drm_gem_object_unreference(&obj->base);
|
|
err:
|
|
return ret;
|
|
}
|
|
|
|
int intel_init_ring_buffer(struct drm_device *dev,
|
|
struct intel_ring_buffer *ring)
|
|
{
|
|
struct drm_i915_gem_object *obj;
|
|
int ret;
|
|
|
|
ring->dev = dev;
|
|
INIT_LIST_HEAD(&ring->active_list);
|
|
INIT_LIST_HEAD(&ring->request_list);
|
|
INIT_LIST_HEAD(&ring->gpu_write_list);
|
|
|
|
spin_lock_init(&ring->irq_lock);
|
|
ring->irq_mask = ~0;
|
|
|
|
if (I915_NEED_GFX_HWS(dev)) {
|
|
ret = init_status_page(ring);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
obj = i915_gem_alloc_object(dev, ring->size);
|
|
if (obj == NULL) {
|
|
DRM_ERROR("Failed to allocate ringbuffer\n");
|
|
ret = -ENOMEM;
|
|
goto err_hws;
|
|
}
|
|
|
|
ring->obj = obj;
|
|
|
|
ret = i915_gem_object_pin(obj, PAGE_SIZE, true);
|
|
if (ret)
|
|
goto err_unref;
|
|
|
|
ring->map.size = ring->size;
|
|
ring->map.offset = dev->agp->base + obj->gtt_offset;
|
|
ring->map.type = 0;
|
|
ring->map.flags = 0;
|
|
ring->map.mtrr = 0;
|
|
|
|
drm_core_ioremap_wc(&ring->map, dev);
|
|
if (ring->map.handle == NULL) {
|
|
DRM_ERROR("Failed to map ringbuffer.\n");
|
|
ret = -EINVAL;
|
|
goto err_unpin;
|
|
}
|
|
|
|
ring->virtual_start = ring->map.handle;
|
|
ret = ring->init(ring);
|
|
if (ret)
|
|
goto err_unmap;
|
|
|
|
/* Workaround an erratum on the i830 which causes a hang if
|
|
* the TAIL pointer points to within the last 2 cachelines
|
|
* of the buffer.
|
|
*/
|
|
ring->effective_size = ring->size;
|
|
if (IS_I830(ring->dev))
|
|
ring->effective_size -= 128;
|
|
|
|
return 0;
|
|
|
|
err_unmap:
|
|
drm_core_ioremapfree(&ring->map, dev);
|
|
err_unpin:
|
|
i915_gem_object_unpin(obj);
|
|
err_unref:
|
|
drm_gem_object_unreference(&obj->base);
|
|
ring->obj = NULL;
|
|
err_hws:
|
|
cleanup_status_page(ring);
|
|
return ret;
|
|
}
|
|
|
|
void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
int ret;
|
|
|
|
if (ring->obj == NULL)
|
|
return;
|
|
|
|
/* Disable the ring buffer. The ring must be idle at this point */
|
|
dev_priv = ring->dev->dev_private;
|
|
ret = intel_wait_ring_buffer(ring, ring->size - 8);
|
|
if (ret)
|
|
DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
|
|
ring->name, ret);
|
|
|
|
I915_WRITE_CTL(ring, 0);
|
|
|
|
drm_core_ioremapfree(&ring->map, ring->dev);
|
|
|
|
i915_gem_object_unpin(ring->obj);
|
|
drm_gem_object_unreference(&ring->obj->base);
|
|
ring->obj = NULL;
|
|
|
|
if (ring->cleanup)
|
|
ring->cleanup(ring);
|
|
|
|
cleanup_status_page(ring);
|
|
}
|
|
|
|
static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
|
|
{
|
|
unsigned int *virt;
|
|
int rem = ring->size - ring->tail;
|
|
|
|
if (ring->space < rem) {
|
|
int ret = intel_wait_ring_buffer(ring, rem);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
virt = (unsigned int *)(ring->virtual_start + ring->tail);
|
|
rem /= 8;
|
|
while (rem--) {
|
|
*virt++ = MI_NOOP;
|
|
*virt++ = MI_NOOP;
|
|
}
|
|
|
|
ring->tail = 0;
|
|
ring->space = ring_space(ring);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n)
|
|
{
|
|
struct drm_device *dev = ring->dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
unsigned long end;
|
|
u32 head;
|
|
|
|
/* If the reported head position has wrapped or hasn't advanced,
|
|
* fallback to the slow and accurate path.
|
|
*/
|
|
head = intel_read_status_page(ring, 4);
|
|
if (head > ring->head) {
|
|
ring->head = head;
|
|
ring->space = ring_space(ring);
|
|
if (ring->space >= n)
|
|
return 0;
|
|
}
|
|
|
|
trace_i915_ring_wait_begin(ring);
|
|
end = jiffies + 3 * HZ;
|
|
do {
|
|
ring->head = I915_READ_HEAD(ring);
|
|
ring->space = ring_space(ring);
|
|
if (ring->space >= n) {
|
|
trace_i915_ring_wait_end(ring);
|
|
return 0;
|
|
}
|
|
|
|
if (dev->primary->master) {
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
|
if (master_priv->sarea_priv)
|
|
master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
|
|
}
|
|
|
|
msleep(1);
|
|
if (atomic_read(&dev_priv->mm.wedged))
|
|
return -EAGAIN;
|
|
} while (!time_after(jiffies, end));
|
|
trace_i915_ring_wait_end(ring);
|
|
return -EBUSY;
|
|
}
|
|
|
|
int intel_ring_begin(struct intel_ring_buffer *ring,
|
|
int num_dwords)
|
|
{
|
|
struct drm_i915_private *dev_priv = ring->dev->dev_private;
|
|
int n = 4*num_dwords;
|
|
int ret;
|
|
|
|
if (unlikely(atomic_read(&dev_priv->mm.wedged)))
|
|
return -EIO;
|
|
|
|
if (unlikely(ring->tail + n > ring->effective_size)) {
|
|
ret = intel_wrap_ring_buffer(ring);
|
|
if (unlikely(ret))
|
|
return ret;
|
|
}
|
|
|
|
if (unlikely(ring->space < n)) {
|
|
ret = intel_wait_ring_buffer(ring, n);
|
|
if (unlikely(ret))
|
|
return ret;
|
|
}
|
|
|
|
ring->space -= n;
|
|
return 0;
|
|
}
|
|
|
|
void intel_ring_advance(struct intel_ring_buffer *ring)
|
|
{
|
|
ring->tail &= ring->size - 1;
|
|
ring->write_tail(ring, ring->tail);
|
|
}
|
|
|
|
static const struct intel_ring_buffer render_ring = {
|
|
.name = "render ring",
|
|
.id = RING_RENDER,
|
|
.mmio_base = RENDER_RING_BASE,
|
|
.size = 32 * PAGE_SIZE,
|
|
.init = init_render_ring,
|
|
.write_tail = ring_write_tail,
|
|
.flush = render_ring_flush,
|
|
.add_request = render_ring_add_request,
|
|
.get_seqno = ring_get_seqno,
|
|
.irq_get = render_ring_get_irq,
|
|
.irq_put = render_ring_put_irq,
|
|
.dispatch_execbuffer = render_ring_dispatch_execbuffer,
|
|
.cleanup = render_ring_cleanup,
|
|
};
|
|
|
|
/* ring buffer for bit-stream decoder */
|
|
|
|
static const struct intel_ring_buffer bsd_ring = {
|
|
.name = "bsd ring",
|
|
.id = RING_BSD,
|
|
.mmio_base = BSD_RING_BASE,
|
|
.size = 32 * PAGE_SIZE,
|
|
.init = init_ring_common,
|
|
.write_tail = ring_write_tail,
|
|
.flush = bsd_ring_flush,
|
|
.add_request = ring_add_request,
|
|
.get_seqno = ring_get_seqno,
|
|
.irq_get = bsd_ring_get_irq,
|
|
.irq_put = bsd_ring_put_irq,
|
|
.dispatch_execbuffer = ring_dispatch_execbuffer,
|
|
};
|
|
|
|
|
|
static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
|
|
u32 value)
|
|
{
|
|
drm_i915_private_t *dev_priv = ring->dev->dev_private;
|
|
|
|
/* Every tail move must follow the sequence below */
|
|
I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE);
|
|
I915_WRITE(GEN6_BSD_RNCID, 0x0);
|
|
|
|
if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0,
|
|
50))
|
|
DRM_ERROR("timed out waiting for IDLE Indicator\n");
|
|
|
|
I915_WRITE_TAIL(ring, value);
|
|
I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK |
|
|
GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE);
|
|
}
|
|
|
|
static int gen6_ring_flush(struct intel_ring_buffer *ring,
|
|
u32 invalidate, u32 flush)
|
|
{
|
|
uint32_t cmd;
|
|
int ret;
|
|
|
|
ret = intel_ring_begin(ring, 4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
cmd = MI_FLUSH_DW;
|
|
if (invalidate & I915_GEM_GPU_DOMAINS)
|
|
cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD;
|
|
intel_ring_emit(ring, cmd);
|
|
intel_ring_emit(ring, 0);
|
|
intel_ring_emit(ring, 0);
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
intel_ring_advance(ring);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
|
|
u32 offset, u32 len)
|
|
{
|
|
int ret;
|
|
|
|
ret = intel_ring_begin(ring, 2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965);
|
|
/* bit0-7 is the length on GEN6+ */
|
|
intel_ring_emit(ring, offset);
|
|
intel_ring_advance(ring);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static bool
|
|
gen6_render_ring_get_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
return gen6_ring_get_irq(ring,
|
|
GT_USER_INTERRUPT,
|
|
GEN6_RENDER_USER_INTERRUPT);
|
|
}
|
|
|
|
static void
|
|
gen6_render_ring_put_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
return gen6_ring_put_irq(ring,
|
|
GT_USER_INTERRUPT,
|
|
GEN6_RENDER_USER_INTERRUPT);
|
|
}
|
|
|
|
static bool
|
|
gen6_bsd_ring_get_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
return gen6_ring_get_irq(ring,
|
|
GT_GEN6_BSD_USER_INTERRUPT,
|
|
GEN6_BSD_USER_INTERRUPT);
|
|
}
|
|
|
|
static void
|
|
gen6_bsd_ring_put_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
return gen6_ring_put_irq(ring,
|
|
GT_GEN6_BSD_USER_INTERRUPT,
|
|
GEN6_BSD_USER_INTERRUPT);
|
|
}
|
|
|
|
/* ring buffer for Video Codec for Gen6+ */
|
|
static const struct intel_ring_buffer gen6_bsd_ring = {
|
|
.name = "gen6 bsd ring",
|
|
.id = RING_BSD,
|
|
.mmio_base = GEN6_BSD_RING_BASE,
|
|
.size = 32 * PAGE_SIZE,
|
|
.init = init_ring_common,
|
|
.write_tail = gen6_bsd_ring_write_tail,
|
|
.flush = gen6_ring_flush,
|
|
.add_request = gen6_add_request,
|
|
.get_seqno = ring_get_seqno,
|
|
.irq_get = gen6_bsd_ring_get_irq,
|
|
.irq_put = gen6_bsd_ring_put_irq,
|
|
.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
|
|
};
|
|
|
|
/* Blitter support (SandyBridge+) */
|
|
|
|
static bool
|
|
blt_ring_get_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
return gen6_ring_get_irq(ring,
|
|
GT_BLT_USER_INTERRUPT,
|
|
GEN6_BLITTER_USER_INTERRUPT);
|
|
}
|
|
|
|
static void
|
|
blt_ring_put_irq(struct intel_ring_buffer *ring)
|
|
{
|
|
gen6_ring_put_irq(ring,
|
|
GT_BLT_USER_INTERRUPT,
|
|
GEN6_BLITTER_USER_INTERRUPT);
|
|
}
|
|
|
|
|
|
/* Workaround for some stepping of SNB,
|
|
* each time when BLT engine ring tail moved,
|
|
* the first command in the ring to be parsed
|
|
* should be MI_BATCH_BUFFER_START
|
|
*/
|
|
#define NEED_BLT_WORKAROUND(dev) \
|
|
(IS_GEN6(dev) && (dev->pdev->revision < 8))
|
|
|
|
static inline struct drm_i915_gem_object *
|
|
to_blt_workaround(struct intel_ring_buffer *ring)
|
|
{
|
|
return ring->private;
|
|
}
|
|
|
|
static int blt_ring_init(struct intel_ring_buffer *ring)
|
|
{
|
|
if (NEED_BLT_WORKAROUND(ring->dev)) {
|
|
struct drm_i915_gem_object *obj;
|
|
u32 *ptr;
|
|
int ret;
|
|
|
|
obj = i915_gem_alloc_object(ring->dev, 4096);
|
|
if (obj == NULL)
|
|
return -ENOMEM;
|
|
|
|
ret = i915_gem_object_pin(obj, 4096, true);
|
|
if (ret) {
|
|
drm_gem_object_unreference(&obj->base);
|
|
return ret;
|
|
}
|
|
|
|
ptr = kmap(obj->pages[0]);
|
|
*ptr++ = MI_BATCH_BUFFER_END;
|
|
*ptr++ = MI_NOOP;
|
|
kunmap(obj->pages[0]);
|
|
|
|
ret = i915_gem_object_set_to_gtt_domain(obj, false);
|
|
if (ret) {
|
|
i915_gem_object_unpin(obj);
|
|
drm_gem_object_unreference(&obj->base);
|
|
return ret;
|
|
}
|
|
|
|
ring->private = obj;
|
|
}
|
|
|
|
return init_ring_common(ring);
|
|
}
|
|
|
|
static int blt_ring_begin(struct intel_ring_buffer *ring,
|
|
int num_dwords)
|
|
{
|
|
if (ring->private) {
|
|
int ret = intel_ring_begin(ring, num_dwords+2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
intel_ring_emit(ring, MI_BATCH_BUFFER_START);
|
|
intel_ring_emit(ring, to_blt_workaround(ring)->gtt_offset);
|
|
|
|
return 0;
|
|
} else
|
|
return intel_ring_begin(ring, 4);
|
|
}
|
|
|
|
static int blt_ring_flush(struct intel_ring_buffer *ring,
|
|
u32 invalidate, u32 flush)
|
|
{
|
|
uint32_t cmd;
|
|
int ret;
|
|
|
|
ret = blt_ring_begin(ring, 4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
cmd = MI_FLUSH_DW;
|
|
if (invalidate & I915_GEM_DOMAIN_RENDER)
|
|
cmd |= MI_INVALIDATE_TLB;
|
|
intel_ring_emit(ring, cmd);
|
|
intel_ring_emit(ring, 0);
|
|
intel_ring_emit(ring, 0);
|
|
intel_ring_emit(ring, MI_NOOP);
|
|
intel_ring_advance(ring);
|
|
return 0;
|
|
}
|
|
|
|
static void blt_ring_cleanup(struct intel_ring_buffer *ring)
|
|
{
|
|
if (!ring->private)
|
|
return;
|
|
|
|
i915_gem_object_unpin(ring->private);
|
|
drm_gem_object_unreference(ring->private);
|
|
ring->private = NULL;
|
|
}
|
|
|
|
static const struct intel_ring_buffer gen6_blt_ring = {
|
|
.name = "blt ring",
|
|
.id = RING_BLT,
|
|
.mmio_base = BLT_RING_BASE,
|
|
.size = 32 * PAGE_SIZE,
|
|
.init = blt_ring_init,
|
|
.write_tail = ring_write_tail,
|
|
.flush = blt_ring_flush,
|
|
.add_request = gen6_add_request,
|
|
.get_seqno = ring_get_seqno,
|
|
.irq_get = blt_ring_get_irq,
|
|
.irq_put = blt_ring_put_irq,
|
|
.dispatch_execbuffer = gen6_ring_dispatch_execbuffer,
|
|
.cleanup = blt_ring_cleanup,
|
|
};
|
|
|
|
int intel_init_render_ring_buffer(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
|
|
|
|
*ring = render_ring;
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
|
ring->add_request = gen6_add_request;
|
|
ring->irq_get = gen6_render_ring_get_irq;
|
|
ring->irq_put = gen6_render_ring_put_irq;
|
|
} else if (IS_GEN5(dev)) {
|
|
ring->add_request = pc_render_add_request;
|
|
ring->get_seqno = pc_render_get_seqno;
|
|
}
|
|
|
|
if (!I915_NEED_GFX_HWS(dev)) {
|
|
ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
|
|
memset(ring->status_page.page_addr, 0, PAGE_SIZE);
|
|
}
|
|
|
|
return intel_init_ring_buffer(dev, ring);
|
|
}
|
|
|
|
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
|
|
|
|
*ring = render_ring;
|
|
if (INTEL_INFO(dev)->gen >= 6) {
|
|
ring->add_request = gen6_add_request;
|
|
ring->irq_get = gen6_render_ring_get_irq;
|
|
ring->irq_put = gen6_render_ring_put_irq;
|
|
} else if (IS_GEN5(dev)) {
|
|
ring->add_request = pc_render_add_request;
|
|
ring->get_seqno = pc_render_get_seqno;
|
|
}
|
|
|
|
ring->dev = dev;
|
|
INIT_LIST_HEAD(&ring->active_list);
|
|
INIT_LIST_HEAD(&ring->request_list);
|
|
INIT_LIST_HEAD(&ring->gpu_write_list);
|
|
|
|
ring->size = size;
|
|
ring->effective_size = ring->size;
|
|
if (IS_I830(ring->dev))
|
|
ring->effective_size -= 128;
|
|
|
|
ring->map.offset = start;
|
|
ring->map.size = size;
|
|
ring->map.type = 0;
|
|
ring->map.flags = 0;
|
|
ring->map.mtrr = 0;
|
|
|
|
drm_core_ioremap_wc(&ring->map, dev);
|
|
if (ring->map.handle == NULL) {
|
|
DRM_ERROR("can not ioremap virtual address for"
|
|
" ring buffer\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
ring->virtual_start = (void __force __iomem *)ring->map.handle;
|
|
return 0;
|
|
}
|
|
|
|
int intel_init_bsd_ring_buffer(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
|
|
|
|
if (IS_GEN6(dev))
|
|
*ring = gen6_bsd_ring;
|
|
else
|
|
*ring = bsd_ring;
|
|
|
|
return intel_init_ring_buffer(dev, ring);
|
|
}
|
|
|
|
int intel_init_blt_ring_buffer(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
|
|
|
|
*ring = gen6_blt_ring;
|
|
|
|
return intel_init_ring_buffer(dev, ring);
|
|
}
|