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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e8dd920776
Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
13 lines
494 B
Makefile
13 lines
494 B
Makefile
#
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# Makefile for Meson specific clk
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#
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-pll.o clk-mpll.o clk-audio-divider.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC) += clk-phase.o
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obj-$(CONFIG_COMMON_CLK_AMLOGIC_AUDIO) += clk-triphase.o
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obj-$(CONFIG_COMMON_CLK_MESON_AO) += meson-aoclk.o
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obj-$(CONFIG_COMMON_CLK_MESON8B) += meson8b.o
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obj-$(CONFIG_COMMON_CLK_GXBB) += gxbb.o gxbb-aoclk.o gxbb-aoclk-32k.o
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obj-$(CONFIG_COMMON_CLK_AXG) += axg.o axg-aoclk.o
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obj-$(CONFIG_COMMON_CLK_REGMAP_MESON) += clk-regmap.o
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