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ae02e5d40d
This layer is responsible for - Enumerating over PCI bus - Inform FW about host readiness - Provide HW interface to transport layer for control and messages - Interrupt handling and routing Original-author: Daniel Drubin <daniel.drubin@intel.com> Reviewed-and-tested-by: Ooi, Joyce <joyce.ooi@intel.com> Tested-by: Grant Likely <grant.likely@secretlab.ca> Tested-by: Rann Bar-On <rb6@duke.edu> Tested-by: Atri Bhattacharya <badshah400@aim.com> Signed-off-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
31 lines
517 B
C
31 lines
517 B
C
#undef TRACE_SYSTEM
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#define TRACE_SYSTEM intel_ish
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#if !defined(_TRACE_INTEL_ISH_H) || defined(TRACE_HEADER_MULTI_READ)
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#define _TRACE_INTEL_ISH_H
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#include <linux/tracepoint.h>
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TRACE_EVENT(ishtp_dump,
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TP_PROTO(const char *message),
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TP_ARGS(message),
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TP_STRUCT__entry(
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__string(message, message)
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),
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TP_fast_assign(
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__assign_str(message, message);
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),
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TP_printk("%s", __get_str(message))
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);
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#endif /* _TRACE_INTEL_ISH_H */
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/* This part must be outside protection */
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#include <trace/define_trace.h>
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