mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-23 14:44:31 +07:00
e8616b6ced
We weren't setting up the vfunc table when initialising the old DRI ringbuffer, leading to such OOPSes as: BUG: unable to handle kernel NULL pointer dereference at (null) IP: [<(null)>] (null) PGD 10c441067 PUD 1185e5067 PMD 0 Oops: 0010 [#1] PREEMPT SMP last sysfs file: /sys/class/dmi/id/chassis_asset_tag CPU 3 Modules linked in: i915 drm_kms_helper drm fb fbdev i2c_algo_bit cfbcopyarea video backlight output cfbimgblt cfbfillrect autofs4 ipv6 nfs lockd fscache nfs_acl auth_rpcgss sunrpc coretemp hwmon_vid mousedev usbhid hid option usb_wwan snd_hda_codec_via asus_atk0110 atl1e usbserial snd_hda_intel snd_hda_codec firmware_class snd_hwdep snd_pcm snd_seq snd_timer snd_seq_device processor parport_pc thermal snd thermal_sys parport 8250_pnp button rng_core rtc_cmos shpchp hwmon rtc_core ehci_hcd pci_hotplug uhci_hcd soundcore tpm_tis i2c_i801 rtc_lib tpm serio_raw snd_page_alloc tpm_bios i2c_core usbcore psmouse intel_agp sg pcspkr sr_mod evdev cdrom ext3 jbd mbcache dm_mod sd_mod ata_piix libata scsi_mod unix Jan 18 15:49:29 lithui kernel: Pid: 3605, comm: Xorg Not tainted 2.6.36.2 #5 P5KPL-CM/System Product Name RIP: 0010:[<0000000000000000>] [<(null)>] (null) RSP: 0018:ffff8801150d1d40 EFLAGS: 00010202 RAX: 000000000001ffff RBX: ffff88011a011b00 RCX: 000000000001a704 RDX: ffff880118566028 RSI: ffff880118566028 RDI: ffff880117876800 RBP: ffff8801150d1d48 R08: ffff8801195fe300 R09: 00000000c0086444 R10: 0000000000000001 R11: 0000000000003206 R12: ffff880117876800 R13: ffff880118566000 R14: ffff880117876820 R15: ffff8801150d1df8 FS: 00007f1038d456e0(0000) GS:ffff880001780000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 0000000000000000 CR3: 00000001187e7000 CR4: 00000000000006e0 DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 DR3: 0000000000000000 DR6: 00000000ffff0ff0 DR7: 0000000000000400 Process Xorg (pid: 3605, threadinfo ffff8801150d0000, task ffff88011b016e40) Stack: ffffffffa043b8e6 ffff8801150d1d98 ffffffffa041768b dead000000000000 <0> 0000000000000048 00007f1023f2a000 0000000000000044 0000000000000008 <0> ffff88010d26bd80 ffff880117876800 ffff8801150d1df8 ffff8801150d1ea8 Call Trace: [<ffffffffa043b8e6>] ? intel_ring_advance+0x16/0x20 [i915] [<ffffffffa041768b>] i915_irq_emit+0x15b/0x240 [i915] [<ffffffffa03ea7b1>] drm_ioctl+0x1f1/0x460 [drm] [<ffffffffa0417530>] ? i915_irq_emit+0x0/0x240 [i915] [<ffffffff810dd8f1>] ? do_sync_read+0xd1/0x120 [<ffffffff81025b1f>] ? do_page_fault+0x1df/0x3d0 [<ffffffff810ed5c7>] do_vfs_ioctl+0x97/0x550 [<ffffffff8115c2ea>] ? security_file_permission+0x7a/0x90 [<ffffffff810edb19>] sys_ioctl+0x99/0xa0 [<ffffffff810024ab>] system_call_fastpath+0x16/0x1b Code: Bad RIP value. RIP [<(null)>] (null) RSP <ffff8801150d1d40> CR2: 0000000000000000 Reported-by: Herbert Xu <herbert@gondor.apana.org.au> Tested-by: Herbert Xu <herbert@gondor.apana.org.au> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=29153 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=23172 Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: stable@kernel.org
2265 lines
57 KiB
C
2265 lines
57 KiB
C
/* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
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*/
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/*
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* Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sub license, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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* IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "drm_crtc_helper.h"
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#include "drm_fb_helper.h"
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#include "intel_drv.h"
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#include "i915_drm.h"
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#include "i915_drv.h"
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#include "i915_trace.h"
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#include "../../../platform/x86/intel_ips.h"
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#include <linux/pci.h>
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#include <linux/vgaarb.h>
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#include <linux/acpi.h>
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#include <linux/pnp.h>
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#include <linux/vga_switcheroo.h>
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#include <linux/slab.h>
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#include <acpi/video.h>
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/**
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* Sets up the hardware status page for devices that need a physical address
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* in the register.
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*/
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static int i915_init_phys_hws(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct intel_ring_buffer *ring = LP_RING(dev_priv);
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/* Program Hardware Status Page */
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dev_priv->status_page_dmah =
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drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE);
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if (!dev_priv->status_page_dmah) {
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DRM_ERROR("Can not allocate hardware status page\n");
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return -ENOMEM;
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}
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ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
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dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
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memset(ring->status_page.page_addr, 0, PAGE_SIZE);
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if (INTEL_INFO(dev)->gen >= 4)
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dev_priv->dma_status_page |= (dev_priv->dma_status_page >> 28) &
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0xf0;
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I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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DRM_DEBUG_DRIVER("Enabled hardware status page\n");
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return 0;
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}
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/**
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* Frees the hardware status page, whether it's a physical address or a virtual
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* address set up by the X Server.
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*/
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static void i915_free_hws(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct intel_ring_buffer *ring = LP_RING(dev_priv);
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if (dev_priv->status_page_dmah) {
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drm_pci_free(dev, dev_priv->status_page_dmah);
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dev_priv->status_page_dmah = NULL;
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}
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if (ring->status_page.gfx_addr) {
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ring->status_page.gfx_addr = 0;
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drm_core_ioremapfree(&dev_priv->hws_map, dev);
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}
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/* Need to rewrite hardware status page */
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I915_WRITE(HWS_PGA, 0x1ffff000);
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}
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void i915_kernel_lost_context(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv;
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struct intel_ring_buffer *ring = LP_RING(dev_priv);
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/*
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* We should never lose context on the ring with modesetting
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* as we don't expose it to userspace
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*/
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if (drm_core_check_feature(dev, DRIVER_MODESET))
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return;
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ring->head = I915_READ_HEAD(ring) & HEAD_ADDR;
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ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
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ring->space = ring->head - (ring->tail + 8);
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if (ring->space < 0)
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ring->space += ring->size;
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if (!dev->primary->master)
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return;
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master_priv = dev->primary->master->driver_priv;
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if (ring->head == ring->tail && master_priv->sarea_priv)
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master_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
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}
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static int i915_dma_cleanup(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int i;
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/* Make sure interrupts are disabled here because the uninstall ioctl
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* may not have been called from userspace and after dev_private
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* is freed, it's too late.
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*/
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if (dev->irq_enabled)
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drm_irq_uninstall(dev);
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mutex_lock(&dev->struct_mutex);
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for (i = 0; i < I915_NUM_RINGS; i++)
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intel_cleanup_ring_buffer(&dev_priv->ring[i]);
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mutex_unlock(&dev->struct_mutex);
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/* Clear the HWS virtual address at teardown */
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if (I915_NEED_GFX_HWS(dev))
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i915_free_hws(dev);
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return 0;
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}
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static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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int ret;
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master_priv->sarea = drm_getsarea(dev);
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if (master_priv->sarea) {
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master_priv->sarea_priv = (drm_i915_sarea_t *)
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((u8 *)master_priv->sarea->handle + init->sarea_priv_offset);
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} else {
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DRM_DEBUG_DRIVER("sarea not found assuming DRI2 userspace\n");
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}
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if (init->ring_size != 0) {
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if (LP_RING(dev_priv)->obj != NULL) {
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i915_dma_cleanup(dev);
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DRM_ERROR("Client tried to initialize ringbuffer in "
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"GEM mode\n");
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return -EINVAL;
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}
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ret = intel_render_ring_init_dri(dev,
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init->ring_start,
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init->ring_size);
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if (ret) {
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i915_dma_cleanup(dev);
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return ret;
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}
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}
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dev_priv->cpp = init->cpp;
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dev_priv->back_offset = init->back_offset;
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dev_priv->front_offset = init->front_offset;
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dev_priv->current_page = 0;
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if (master_priv->sarea_priv)
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master_priv->sarea_priv->pf_current_page = 0;
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/* Allow hardware batchbuffers unless told otherwise.
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*/
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dev_priv->allow_batchbuffer = 1;
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return 0;
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}
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static int i915_dma_resume(struct drm_device * dev)
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{
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drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
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struct intel_ring_buffer *ring = LP_RING(dev_priv);
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DRM_DEBUG_DRIVER("%s\n", __func__);
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if (ring->map.handle == NULL) {
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DRM_ERROR("can not ioremap virtual address for"
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" ring buffer\n");
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return -ENOMEM;
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}
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/* Program Hardware Status Page */
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if (!ring->status_page.page_addr) {
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DRM_ERROR("Can not find hardware status page\n");
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return -EINVAL;
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}
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DRM_DEBUG_DRIVER("hw status page @ %p\n",
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ring->status_page.page_addr);
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if (ring->status_page.gfx_addr != 0)
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intel_ring_setup_status_page(ring);
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else
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I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
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DRM_DEBUG_DRIVER("Enabled hardware status page\n");
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return 0;
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}
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static int i915_dma_init(struct drm_device *dev, void *data,
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struct drm_file *file_priv)
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{
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drm_i915_init_t *init = data;
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int retcode = 0;
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switch (init->func) {
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case I915_INIT_DMA:
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retcode = i915_initialize(dev, init);
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break;
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case I915_CLEANUP_DMA:
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retcode = i915_dma_cleanup(dev);
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break;
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case I915_RESUME_DMA:
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retcode = i915_dma_resume(dev);
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break;
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default:
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retcode = -EINVAL;
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break;
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}
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return retcode;
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}
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/* Implement basically the same security restrictions as hardware does
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* for MI_BATCH_NON_SECURE. These can be made stricter at any time.
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*
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* Most of the calculations below involve calculating the size of a
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* particular instruction. It's important to get the size right as
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* that tells us where the next instruction to check is. Any illegal
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* instruction detected will be given a size of zero, which is a
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* signal to abort the rest of the buffer.
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*/
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static int validate_cmd(int cmd)
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{
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switch (((cmd >> 29) & 0x7)) {
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case 0x0:
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switch ((cmd >> 23) & 0x3f) {
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case 0x0:
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return 1; /* MI_NOOP */
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case 0x4:
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return 1; /* MI_FLUSH */
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default:
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return 0; /* disallow everything else */
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}
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break;
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case 0x1:
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return 0; /* reserved */
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case 0x2:
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return (cmd & 0xff) + 2; /* 2d commands */
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case 0x3:
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if (((cmd >> 24) & 0x1f) <= 0x18)
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return 1;
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switch ((cmd >> 24) & 0x1f) {
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case 0x1c:
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return 1;
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case 0x1d:
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switch ((cmd >> 16) & 0xff) {
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case 0x3:
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return (cmd & 0x1f) + 2;
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case 0x4:
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return (cmd & 0xf) + 2;
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default:
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return (cmd & 0xffff) + 2;
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}
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case 0x1e:
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if (cmd & (1 << 23))
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return (cmd & 0xffff) + 1;
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else
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return 1;
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case 0x1f:
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if ((cmd & (1 << 23)) == 0) /* inline vertices */
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return (cmd & 0x1ffff) + 2;
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else if (cmd & (1 << 17)) /* indirect random */
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if ((cmd & 0xffff) == 0)
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return 0; /* unknown length, too hard */
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else
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return (((cmd & 0xffff) + 1) / 2) + 1;
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else
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return 2; /* indirect sequential */
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default:
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return 0;
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}
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default:
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return 0;
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}
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return 0;
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}
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static int i915_emit_cmds(struct drm_device * dev, int *buffer, int dwords)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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int i, ret;
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if ((dwords+1) * sizeof(int) >= LP_RING(dev_priv)->size - 8)
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return -EINVAL;
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for (i = 0; i < dwords;) {
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int sz = validate_cmd(buffer[i]);
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if (sz == 0 || i + sz > dwords)
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return -EINVAL;
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i += sz;
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}
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ret = BEGIN_LP_RING((dwords+1)&~1);
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if (ret)
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return ret;
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for (i = 0; i < dwords; i++)
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OUT_RING(buffer[i]);
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if (dwords & 1)
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OUT_RING(0);
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ADVANCE_LP_RING();
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return 0;
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}
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int
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i915_emit_box(struct drm_device *dev,
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struct drm_clip_rect *box,
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int DR1, int DR4)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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int ret;
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if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
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box->y2 <= 0 || box->x2 <= 0) {
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DRM_ERROR("Bad box %d,%d..%d,%d\n",
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box->x1, box->y1, box->x2, box->y2);
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return -EINVAL;
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}
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if (INTEL_INFO(dev)->gen >= 4) {
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ret = BEGIN_LP_RING(4);
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if (ret)
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return ret;
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OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
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OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
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OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
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OUT_RING(DR4);
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} else {
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ret = BEGIN_LP_RING(6);
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if (ret)
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return ret;
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OUT_RING(GFX_OP_DRAWRECT_INFO);
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OUT_RING(DR1);
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OUT_RING((box->x1 & 0xffff) | (box->y1 << 16));
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OUT_RING(((box->x2 - 1) & 0xffff) | ((box->y2 - 1) << 16));
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OUT_RING(DR4);
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OUT_RING(0);
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}
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ADVANCE_LP_RING();
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return 0;
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}
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/* XXX: Emitting the counter should really be moved to part of the IRQ
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* emit. For now, do it in both places:
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*/
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static void i915_emit_breadcrumb(struct drm_device *dev)
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{
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drm_i915_private_t *dev_priv = dev->dev_private;
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struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
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dev_priv->counter++;
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if (dev_priv->counter > 0x7FFFFFFFUL)
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dev_priv->counter = 0;
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if (master_priv->sarea_priv)
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master_priv->sarea_priv->last_enqueue = dev_priv->counter;
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if (BEGIN_LP_RING(4) == 0) {
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OUT_RING(MI_STORE_DWORD_INDEX);
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OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
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OUT_RING(dev_priv->counter);
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OUT_RING(0);
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ADVANCE_LP_RING();
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}
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}
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static int i915_dispatch_cmdbuffer(struct drm_device * dev,
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drm_i915_cmdbuffer_t *cmd,
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struct drm_clip_rect *cliprects,
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void *cmdbuf)
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{
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int nbox = cmd->num_cliprects;
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int i = 0, count, ret;
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|
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if (cmd->sz & 0x3) {
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DRM_ERROR("alignment");
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return -EINVAL;
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}
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i915_kernel_lost_context(dev);
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count = nbox ? nbox : 1;
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for (i = 0; i < count; i++) {
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if (i < nbox) {
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|
ret = i915_emit_box(dev, &cliprects[i],
|
|
cmd->DR1, cmd->DR4);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = i915_emit_cmds(dev, cmdbuf, cmd->sz / 4);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
i915_emit_breadcrumb(dev);
|
|
return 0;
|
|
}
|
|
|
|
static int i915_dispatch_batchbuffer(struct drm_device * dev,
|
|
drm_i915_batchbuffer_t * batch,
|
|
struct drm_clip_rect *cliprects)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int nbox = batch->num_cliprects;
|
|
int i, count, ret;
|
|
|
|
if ((batch->start | batch->used) & 0x7) {
|
|
DRM_ERROR("alignment");
|
|
return -EINVAL;
|
|
}
|
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
count = nbox ? nbox : 1;
|
|
for (i = 0; i < count; i++) {
|
|
if (i < nbox) {
|
|
ret = i915_emit_box(dev, &cliprects[i],
|
|
batch->DR1, batch->DR4);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
if (!IS_I830(dev) && !IS_845G(dev)) {
|
|
ret = BEGIN_LP_RING(2);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4) {
|
|
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
|
|
OUT_RING(batch->start);
|
|
} else {
|
|
OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
|
}
|
|
} else {
|
|
ret = BEGIN_LP_RING(4);
|
|
if (ret)
|
|
return ret;
|
|
|
|
OUT_RING(MI_BATCH_BUFFER);
|
|
OUT_RING(batch->start | MI_BATCH_NON_SECURE);
|
|
OUT_RING(batch->start + batch->used - 4);
|
|
OUT_RING(0);
|
|
}
|
|
ADVANCE_LP_RING();
|
|
}
|
|
|
|
|
|
if (IS_G4X(dev) || IS_GEN5(dev)) {
|
|
if (BEGIN_LP_RING(2) == 0) {
|
|
OUT_RING(MI_FLUSH | MI_NO_WRITE_FLUSH | MI_INVALIDATE_ISP);
|
|
OUT_RING(MI_NOOP);
|
|
ADVANCE_LP_RING();
|
|
}
|
|
}
|
|
|
|
i915_emit_breadcrumb(dev);
|
|
return 0;
|
|
}
|
|
|
|
static int i915_dispatch_flip(struct drm_device * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
struct drm_i915_master_private *master_priv =
|
|
dev->primary->master->driver_priv;
|
|
int ret;
|
|
|
|
if (!master_priv->sarea_priv)
|
|
return -EINVAL;
|
|
|
|
DRM_DEBUG_DRIVER("%s: page=%d pfCurrentPage=%d\n",
|
|
__func__,
|
|
dev_priv->current_page,
|
|
master_priv->sarea_priv->pf_current_page);
|
|
|
|
i915_kernel_lost_context(dev);
|
|
|
|
ret = BEGIN_LP_RING(10);
|
|
if (ret)
|
|
return ret;
|
|
|
|
OUT_RING(MI_FLUSH | MI_READ_FLUSH);
|
|
OUT_RING(0);
|
|
|
|
OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
|
|
OUT_RING(0);
|
|
if (dev_priv->current_page == 0) {
|
|
OUT_RING(dev_priv->back_offset);
|
|
dev_priv->current_page = 1;
|
|
} else {
|
|
OUT_RING(dev_priv->front_offset);
|
|
dev_priv->current_page = 0;
|
|
}
|
|
OUT_RING(0);
|
|
|
|
OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
|
|
OUT_RING(0);
|
|
|
|
ADVANCE_LP_RING();
|
|
|
|
master_priv->sarea_priv->last_enqueue = dev_priv->counter++;
|
|
|
|
if (BEGIN_LP_RING(4) == 0) {
|
|
OUT_RING(MI_STORE_DWORD_INDEX);
|
|
OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
|
|
OUT_RING(dev_priv->counter);
|
|
OUT_RING(0);
|
|
ADVANCE_LP_RING();
|
|
}
|
|
|
|
master_priv->sarea_priv->pf_current_page = dev_priv->current_page;
|
|
return 0;
|
|
}
|
|
|
|
static int i915_quiescent(struct drm_device *dev)
|
|
{
|
|
struct intel_ring_buffer *ring = LP_RING(dev->dev_private);
|
|
|
|
i915_kernel_lost_context(dev);
|
|
return intel_wait_ring_buffer(ring, ring->size - 8);
|
|
}
|
|
|
|
static int i915_flush_ioctl(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
int ret;
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ret = i915_quiescent(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_batchbuffer(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
master_priv->sarea_priv;
|
|
drm_i915_batchbuffer_t *batch = data;
|
|
int ret;
|
|
struct drm_clip_rect *cliprects = NULL;
|
|
|
|
if (!dev_priv->allow_batchbuffer) {
|
|
DRM_ERROR("Batchbuffer ioctl disabled\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
DRM_DEBUG_DRIVER("i915 batchbuffer, start %x used %d cliprects %d\n",
|
|
batch->start, batch->used, batch->num_cliprects);
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
if (batch->num_cliprects < 0)
|
|
return -EINVAL;
|
|
|
|
if (batch->num_cliprects) {
|
|
cliprects = kcalloc(batch->num_cliprects,
|
|
sizeof(struct drm_clip_rect),
|
|
GFP_KERNEL);
|
|
if (cliprects == NULL)
|
|
return -ENOMEM;
|
|
|
|
ret = copy_from_user(cliprects, batch->cliprects,
|
|
batch->num_cliprects *
|
|
sizeof(struct drm_clip_rect));
|
|
if (ret != 0) {
|
|
ret = -EFAULT;
|
|
goto fail_free;
|
|
}
|
|
}
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ret = i915_dispatch_batchbuffer(dev, batch, cliprects);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
if (sarea_priv)
|
|
sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
|
|
fail_free:
|
|
kfree(cliprects);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_cmdbuffer(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
|
|
struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
|
|
drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
|
|
master_priv->sarea_priv;
|
|
drm_i915_cmdbuffer_t *cmdbuf = data;
|
|
struct drm_clip_rect *cliprects = NULL;
|
|
void *batch_data;
|
|
int ret;
|
|
|
|
DRM_DEBUG_DRIVER("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
|
|
cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
if (cmdbuf->num_cliprects < 0)
|
|
return -EINVAL;
|
|
|
|
batch_data = kmalloc(cmdbuf->sz, GFP_KERNEL);
|
|
if (batch_data == NULL)
|
|
return -ENOMEM;
|
|
|
|
ret = copy_from_user(batch_data, cmdbuf->buf, cmdbuf->sz);
|
|
if (ret != 0) {
|
|
ret = -EFAULT;
|
|
goto fail_batch_free;
|
|
}
|
|
|
|
if (cmdbuf->num_cliprects) {
|
|
cliprects = kcalloc(cmdbuf->num_cliprects,
|
|
sizeof(struct drm_clip_rect), GFP_KERNEL);
|
|
if (cliprects == NULL) {
|
|
ret = -ENOMEM;
|
|
goto fail_batch_free;
|
|
}
|
|
|
|
ret = copy_from_user(cliprects, cmdbuf->cliprects,
|
|
cmdbuf->num_cliprects *
|
|
sizeof(struct drm_clip_rect));
|
|
if (ret != 0) {
|
|
ret = -EFAULT;
|
|
goto fail_clip_free;
|
|
}
|
|
}
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ret = i915_dispatch_cmdbuffer(dev, cmdbuf, cliprects, batch_data);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
if (ret) {
|
|
DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
|
|
goto fail_clip_free;
|
|
}
|
|
|
|
if (sarea_priv)
|
|
sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
|
|
|
|
fail_clip_free:
|
|
kfree(cliprects);
|
|
fail_batch_free:
|
|
kfree(batch_data);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_flip_bufs(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
int ret;
|
|
|
|
DRM_DEBUG_DRIVER("%s\n", __func__);
|
|
|
|
RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ret = i915_dispatch_flip(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int i915_getparam(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_getparam_t *param = data;
|
|
int value;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (param->param) {
|
|
case I915_PARAM_IRQ_ACTIVE:
|
|
value = dev->pdev->irq ? 1 : 0;
|
|
break;
|
|
case I915_PARAM_ALLOW_BATCHBUFFER:
|
|
value = dev_priv->allow_batchbuffer ? 1 : 0;
|
|
break;
|
|
case I915_PARAM_LAST_DISPATCH:
|
|
value = READ_BREADCRUMB(dev_priv);
|
|
break;
|
|
case I915_PARAM_CHIPSET_ID:
|
|
value = dev->pci_device;
|
|
break;
|
|
case I915_PARAM_HAS_GEM:
|
|
value = dev_priv->has_gem;
|
|
break;
|
|
case I915_PARAM_NUM_FENCES_AVAIL:
|
|
value = dev_priv->num_fence_regs - dev_priv->fence_reg_start;
|
|
break;
|
|
case I915_PARAM_HAS_OVERLAY:
|
|
value = dev_priv->overlay ? 1 : 0;
|
|
break;
|
|
case I915_PARAM_HAS_PAGEFLIPPING:
|
|
value = 1;
|
|
break;
|
|
case I915_PARAM_HAS_EXECBUF2:
|
|
/* depends on GEM */
|
|
value = dev_priv->has_gem;
|
|
break;
|
|
case I915_PARAM_HAS_BSD:
|
|
value = HAS_BSD(dev);
|
|
break;
|
|
case I915_PARAM_HAS_BLT:
|
|
value = HAS_BLT(dev);
|
|
break;
|
|
case I915_PARAM_HAS_RELAXED_FENCING:
|
|
value = 1;
|
|
break;
|
|
case I915_PARAM_HAS_COHERENT_RINGS:
|
|
value = 1;
|
|
break;
|
|
case I915_PARAM_HAS_EXEC_CONSTANTS:
|
|
value = INTEL_INFO(dev)->gen >= 4;
|
|
break;
|
|
default:
|
|
DRM_DEBUG_DRIVER("Unknown parameter %d\n",
|
|
param->param);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
|
|
DRM_ERROR("DRM_COPY_TO_USER failed\n");
|
|
return -EFAULT;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_setparam(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_setparam_t *param = data;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (param->param) {
|
|
case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
|
|
break;
|
|
case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
|
|
dev_priv->tex_lru_log_granularity = param->value;
|
|
break;
|
|
case I915_SETPARAM_ALLOW_BATCHBUFFER:
|
|
dev_priv->allow_batchbuffer = param->value;
|
|
break;
|
|
case I915_SETPARAM_NUM_USED_FENCES:
|
|
if (param->value > dev_priv->num_fence_regs ||
|
|
param->value < 0)
|
|
return -EINVAL;
|
|
/* Userspace can use first N regs */
|
|
dev_priv->fence_reg_start = param->value;
|
|
break;
|
|
default:
|
|
DRM_DEBUG_DRIVER("unknown parameter %d\n",
|
|
param->param);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int i915_set_status_page(struct drm_device *dev, void *data,
|
|
struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
drm_i915_hws_addr_t *hws = data;
|
|
struct intel_ring_buffer *ring = LP_RING(dev_priv);
|
|
|
|
if (!I915_NEED_GFX_HWS(dev))
|
|
return -EINVAL;
|
|
|
|
if (!dev_priv) {
|
|
DRM_ERROR("called with no initialization\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
WARN(1, "tried to set status page when mode setting active\n");
|
|
return 0;
|
|
}
|
|
|
|
DRM_DEBUG_DRIVER("set status page addr 0x%08x\n", (u32)hws->addr);
|
|
|
|
ring->status_page.gfx_addr = hws->addr & (0x1ffff<<12);
|
|
|
|
dev_priv->hws_map.offset = dev->agp->base + hws->addr;
|
|
dev_priv->hws_map.size = 4*1024;
|
|
dev_priv->hws_map.type = 0;
|
|
dev_priv->hws_map.flags = 0;
|
|
dev_priv->hws_map.mtrr = 0;
|
|
|
|
drm_core_ioremap_wc(&dev_priv->hws_map, dev);
|
|
if (dev_priv->hws_map.handle == NULL) {
|
|
i915_dma_cleanup(dev);
|
|
ring->status_page.gfx_addr = 0;
|
|
DRM_ERROR("can not ioremap virtual address for"
|
|
" G33 hw status page\n");
|
|
return -ENOMEM;
|
|
}
|
|
ring->status_page.page_addr = dev_priv->hws_map.handle;
|
|
memset(ring->status_page.page_addr, 0, PAGE_SIZE);
|
|
I915_WRITE(HWS_PGA, ring->status_page.gfx_addr);
|
|
|
|
DRM_DEBUG_DRIVER("load hws HWS_PGA with gfx mem 0x%x\n",
|
|
ring->status_page.gfx_addr);
|
|
DRM_DEBUG_DRIVER("load hws at %p\n",
|
|
ring->status_page.page_addr);
|
|
return 0;
|
|
}
|
|
|
|
static int i915_get_bridge_dev(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
dev_priv->bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0,0));
|
|
if (!dev_priv->bridge_dev) {
|
|
DRM_ERROR("bridge device not found\n");
|
|
return -1;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
#define MCHBAR_I915 0x44
|
|
#define MCHBAR_I965 0x48
|
|
#define MCHBAR_SIZE (4*4096)
|
|
|
|
#define DEVEN_REG 0x54
|
|
#define DEVEN_MCHBAR_EN (1 << 28)
|
|
|
|
/* Allocate space for the MCH regs if needed, return nonzero on error */
|
|
static int
|
|
intel_alloc_mchbar_resource(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
int reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
|
|
u32 temp_lo, temp_hi = 0;
|
|
u64 mchbar_addr;
|
|
int ret;
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
|
pci_read_config_dword(dev_priv->bridge_dev, reg + 4, &temp_hi);
|
|
pci_read_config_dword(dev_priv->bridge_dev, reg, &temp_lo);
|
|
mchbar_addr = ((u64)temp_hi << 32) | temp_lo;
|
|
|
|
/* If ACPI doesn't have it, assume we need to allocate it ourselves */
|
|
#ifdef CONFIG_PNP
|
|
if (mchbar_addr &&
|
|
pnp_range_reserved(mchbar_addr, mchbar_addr + MCHBAR_SIZE))
|
|
return 0;
|
|
#endif
|
|
|
|
/* Get some space for it */
|
|
dev_priv->mch_res.name = "i915 MCHBAR";
|
|
dev_priv->mch_res.flags = IORESOURCE_MEM;
|
|
ret = pci_bus_alloc_resource(dev_priv->bridge_dev->bus,
|
|
&dev_priv->mch_res,
|
|
MCHBAR_SIZE, MCHBAR_SIZE,
|
|
PCIBIOS_MIN_MEM,
|
|
0, pcibios_align_resource,
|
|
dev_priv->bridge_dev);
|
|
if (ret) {
|
|
DRM_DEBUG_DRIVER("failed bus alloc: %d\n", ret);
|
|
dev_priv->mch_res.start = 0;
|
|
return ret;
|
|
}
|
|
|
|
if (INTEL_INFO(dev)->gen >= 4)
|
|
pci_write_config_dword(dev_priv->bridge_dev, reg + 4,
|
|
upper_32_bits(dev_priv->mch_res.start));
|
|
|
|
pci_write_config_dword(dev_priv->bridge_dev, reg,
|
|
lower_32_bits(dev_priv->mch_res.start));
|
|
return 0;
|
|
}
|
|
|
|
/* Setup MCHBAR if possible, return true if we should disable it again */
|
|
static void
|
|
intel_setup_mchbar(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
|
|
u32 temp;
|
|
bool enabled;
|
|
|
|
dev_priv->mchbar_need_disable = false;
|
|
|
|
if (IS_I915G(dev) || IS_I915GM(dev)) {
|
|
pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
|
|
enabled = !!(temp & DEVEN_MCHBAR_EN);
|
|
} else {
|
|
pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
|
|
enabled = temp & 1;
|
|
}
|
|
|
|
/* If it's already enabled, don't have to do anything */
|
|
if (enabled)
|
|
return;
|
|
|
|
if (intel_alloc_mchbar_resource(dev))
|
|
return;
|
|
|
|
dev_priv->mchbar_need_disable = true;
|
|
|
|
/* Space is allocated or reserved, so enable it. */
|
|
if (IS_I915G(dev) || IS_I915GM(dev)) {
|
|
pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG,
|
|
temp | DEVEN_MCHBAR_EN);
|
|
} else {
|
|
pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
|
|
pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp | 1);
|
|
}
|
|
}
|
|
|
|
static void
|
|
intel_teardown_mchbar(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
int mchbar_reg = INTEL_INFO(dev)->gen >= 4 ? MCHBAR_I965 : MCHBAR_I915;
|
|
u32 temp;
|
|
|
|
if (dev_priv->mchbar_need_disable) {
|
|
if (IS_I915G(dev) || IS_I915GM(dev)) {
|
|
pci_read_config_dword(dev_priv->bridge_dev, DEVEN_REG, &temp);
|
|
temp &= ~DEVEN_MCHBAR_EN;
|
|
pci_write_config_dword(dev_priv->bridge_dev, DEVEN_REG, temp);
|
|
} else {
|
|
pci_read_config_dword(dev_priv->bridge_dev, mchbar_reg, &temp);
|
|
temp &= ~1;
|
|
pci_write_config_dword(dev_priv->bridge_dev, mchbar_reg, temp);
|
|
}
|
|
}
|
|
|
|
if (dev_priv->mch_res.start)
|
|
release_resource(&dev_priv->mch_res);
|
|
}
|
|
|
|
#define PTE_ADDRESS_MASK 0xfffff000
|
|
#define PTE_ADDRESS_MASK_HIGH 0x000000f0 /* i915+ */
|
|
#define PTE_MAPPING_TYPE_UNCACHED (0 << 1)
|
|
#define PTE_MAPPING_TYPE_DCACHE (1 << 1) /* i830 only */
|
|
#define PTE_MAPPING_TYPE_CACHED (3 << 1)
|
|
#define PTE_MAPPING_TYPE_MASK (3 << 1)
|
|
#define PTE_VALID (1 << 0)
|
|
|
|
/**
|
|
* i915_stolen_to_phys - take an offset into stolen memory and turn it into
|
|
* a physical one
|
|
* @dev: drm device
|
|
* @offset: address to translate
|
|
*
|
|
* Some chip functions require allocations from stolen space and need the
|
|
* physical address of the memory in question.
|
|
*/
|
|
static unsigned long i915_stolen_to_phys(struct drm_device *dev, u32 offset)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct pci_dev *pdev = dev_priv->bridge_dev;
|
|
u32 base;
|
|
|
|
#if 0
|
|
/* On the machines I have tested the Graphics Base of Stolen Memory
|
|
* is unreliable, so compute the base by subtracting the stolen memory
|
|
* from the Top of Low Usable DRAM which is where the BIOS places
|
|
* the graphics stolen memory.
|
|
*/
|
|
if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
|
|
/* top 32bits are reserved = 0 */
|
|
pci_read_config_dword(pdev, 0xA4, &base);
|
|
} else {
|
|
/* XXX presume 8xx is the same as i915 */
|
|
pci_bus_read_config_dword(pdev->bus, 2, 0x5C, &base);
|
|
}
|
|
#else
|
|
if (INTEL_INFO(dev)->gen > 3 || IS_G33(dev)) {
|
|
u16 val;
|
|
pci_read_config_word(pdev, 0xb0, &val);
|
|
base = val >> 4 << 20;
|
|
} else {
|
|
u8 val;
|
|
pci_read_config_byte(pdev, 0x9c, &val);
|
|
base = val >> 3 << 27;
|
|
}
|
|
base -= dev_priv->mm.gtt->stolen_size;
|
|
#endif
|
|
|
|
return base + offset;
|
|
}
|
|
|
|
static void i915_warn_stolen(struct drm_device *dev)
|
|
{
|
|
DRM_ERROR("not enough stolen space for compressed buffer, disabling\n");
|
|
DRM_ERROR("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
|
|
}
|
|
|
|
static void i915_setup_compression(struct drm_device *dev, int size)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_mm_node *compressed_fb, *uninitialized_var(compressed_llb);
|
|
unsigned long cfb_base;
|
|
unsigned long ll_base = 0;
|
|
|
|
compressed_fb = drm_mm_search_free(&dev_priv->mm.stolen, size, 4096, 0);
|
|
if (compressed_fb)
|
|
compressed_fb = drm_mm_get_block(compressed_fb, size, 4096);
|
|
if (!compressed_fb)
|
|
goto err;
|
|
|
|
cfb_base = i915_stolen_to_phys(dev, compressed_fb->start);
|
|
if (!cfb_base)
|
|
goto err_fb;
|
|
|
|
if (!(IS_GM45(dev) || HAS_PCH_SPLIT(dev))) {
|
|
compressed_llb = drm_mm_search_free(&dev_priv->mm.stolen,
|
|
4096, 4096, 0);
|
|
if (compressed_llb)
|
|
compressed_llb = drm_mm_get_block(compressed_llb,
|
|
4096, 4096);
|
|
if (!compressed_llb)
|
|
goto err_fb;
|
|
|
|
ll_base = i915_stolen_to_phys(dev, compressed_llb->start);
|
|
if (!ll_base)
|
|
goto err_llb;
|
|
}
|
|
|
|
dev_priv->cfb_size = size;
|
|
|
|
intel_disable_fbc(dev);
|
|
dev_priv->compressed_fb = compressed_fb;
|
|
if (HAS_PCH_SPLIT(dev))
|
|
I915_WRITE(ILK_DPFC_CB_BASE, compressed_fb->start);
|
|
else if (IS_GM45(dev)) {
|
|
I915_WRITE(DPFC_CB_BASE, compressed_fb->start);
|
|
} else {
|
|
I915_WRITE(FBC_CFB_BASE, cfb_base);
|
|
I915_WRITE(FBC_LL_BASE, ll_base);
|
|
dev_priv->compressed_llb = compressed_llb;
|
|
}
|
|
|
|
DRM_DEBUG_KMS("FBC base 0x%08lx, ll base 0x%08lx, size %dM\n",
|
|
cfb_base, ll_base, size >> 20);
|
|
return;
|
|
|
|
err_llb:
|
|
drm_mm_put_block(compressed_llb);
|
|
err_fb:
|
|
drm_mm_put_block(compressed_fb);
|
|
err:
|
|
dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
|
|
i915_warn_stolen(dev);
|
|
}
|
|
|
|
static void i915_cleanup_compression(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
drm_mm_put_block(dev_priv->compressed_fb);
|
|
if (dev_priv->compressed_llb)
|
|
drm_mm_put_block(dev_priv->compressed_llb);
|
|
}
|
|
|
|
/* true = enable decode, false = disable decoder */
|
|
static unsigned int i915_vga_set_decode(void *cookie, bool state)
|
|
{
|
|
struct drm_device *dev = cookie;
|
|
|
|
intel_modeset_vga_set_state(dev, state);
|
|
if (state)
|
|
return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
|
|
VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
else
|
|
return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
|
|
}
|
|
|
|
static void i915_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
pm_message_t pmm = { .event = PM_EVENT_SUSPEND };
|
|
if (state == VGA_SWITCHEROO_ON) {
|
|
printk(KERN_INFO "i915: switched on\n");
|
|
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
|
/* i915 resume handler doesn't set to D0 */
|
|
pci_set_power_state(dev->pdev, PCI_D0);
|
|
i915_resume(dev);
|
|
dev->switch_power_state = DRM_SWITCH_POWER_ON;
|
|
} else {
|
|
printk(KERN_ERR "i915: switched off\n");
|
|
dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
|
|
i915_suspend(dev, pmm);
|
|
dev->switch_power_state = DRM_SWITCH_POWER_OFF;
|
|
}
|
|
}
|
|
|
|
static bool i915_switcheroo_can_switch(struct pci_dev *pdev)
|
|
{
|
|
struct drm_device *dev = pci_get_drvdata(pdev);
|
|
bool can_switch;
|
|
|
|
spin_lock(&dev->count_lock);
|
|
can_switch = (dev->open_count == 0);
|
|
spin_unlock(&dev->count_lock);
|
|
return can_switch;
|
|
}
|
|
|
|
static int i915_load_modeset_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
unsigned long prealloc_size, gtt_size, mappable_size;
|
|
int ret = 0;
|
|
|
|
prealloc_size = dev_priv->mm.gtt->stolen_size;
|
|
gtt_size = dev_priv->mm.gtt->gtt_total_entries << PAGE_SHIFT;
|
|
mappable_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
|
|
|
|
/* Basic memrange allocator for stolen space */
|
|
drm_mm_init(&dev_priv->mm.stolen, 0, prealloc_size);
|
|
|
|
/* Let GEM Manage all of the aperture.
|
|
*
|
|
* However, leave one page at the end still bound to the scratch page.
|
|
* There are a number of places where the hardware apparently
|
|
* prefetches past the end of the object, and we've seen multiple
|
|
* hangs with the GPU head pointer stuck in a batchbuffer bound
|
|
* at the last page of the aperture. One page should be enough to
|
|
* keep any prefetching inside of the aperture.
|
|
*/
|
|
i915_gem_do_init(dev, 0, mappable_size, gtt_size - PAGE_SIZE);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ret = i915_gem_init_ringbuffer(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
if (ret)
|
|
goto out;
|
|
|
|
/* Try to set up FBC with a reasonable compressed buffer size */
|
|
if (I915_HAS_FBC(dev) && i915_powersave) {
|
|
int cfb_size;
|
|
|
|
/* Leave 1M for line length buffer & misc. */
|
|
|
|
/* Try to get a 32M buffer... */
|
|
if (prealloc_size > (36*1024*1024))
|
|
cfb_size = 32*1024*1024;
|
|
else /* fall back to 7/8 of the stolen space */
|
|
cfb_size = prealloc_size * 7 / 8;
|
|
i915_setup_compression(dev, cfb_size);
|
|
}
|
|
|
|
/* Allow hardware batchbuffers unless told otherwise. */
|
|
dev_priv->allow_batchbuffer = 1;
|
|
|
|
ret = intel_parse_bios(dev);
|
|
if (ret)
|
|
DRM_INFO("failed to find VBIOS tables\n");
|
|
|
|
/* if we have > 1 VGA cards, then disable the radeon VGA resources */
|
|
ret = vga_client_register(dev->pdev, dev, NULL, i915_vga_set_decode);
|
|
if (ret)
|
|
goto cleanup_ringbuffer;
|
|
|
|
intel_register_dsm_handler();
|
|
|
|
ret = vga_switcheroo_register_client(dev->pdev,
|
|
i915_switcheroo_set_state,
|
|
NULL,
|
|
i915_switcheroo_can_switch);
|
|
if (ret)
|
|
goto cleanup_vga_client;
|
|
|
|
/* IIR "flip pending" bit means done if this bit is set */
|
|
if (IS_GEN3(dev) && (I915_READ(ECOSKPD) & ECO_FLIP_DONE))
|
|
dev_priv->flip_pending_is_done = true;
|
|
|
|
intel_modeset_init(dev);
|
|
|
|
ret = drm_irq_install(dev);
|
|
if (ret)
|
|
goto cleanup_vga_switcheroo;
|
|
|
|
/* Always safe in the mode setting case. */
|
|
/* FIXME: do pre/post-mode set stuff in core KMS code */
|
|
dev->vblank_disable_allowed = 1;
|
|
|
|
ret = intel_fbdev_init(dev);
|
|
if (ret)
|
|
goto cleanup_irq;
|
|
|
|
drm_kms_helper_poll_init(dev);
|
|
|
|
/* We're off and running w/KMS */
|
|
dev_priv->mm.suspended = 0;
|
|
|
|
return 0;
|
|
|
|
cleanup_irq:
|
|
drm_irq_uninstall(dev);
|
|
cleanup_vga_switcheroo:
|
|
vga_switcheroo_unregister_client(dev->pdev);
|
|
cleanup_vga_client:
|
|
vga_client_register(dev->pdev, NULL, NULL, NULL);
|
|
cleanup_ringbuffer:
|
|
mutex_lock(&dev->struct_mutex);
|
|
i915_gem_cleanup_ringbuffer(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
out:
|
|
return ret;
|
|
}
|
|
|
|
int i915_master_create(struct drm_device *dev, struct drm_master *master)
|
|
{
|
|
struct drm_i915_master_private *master_priv;
|
|
|
|
master_priv = kzalloc(sizeof(*master_priv), GFP_KERNEL);
|
|
if (!master_priv)
|
|
return -ENOMEM;
|
|
|
|
master->driver_priv = master_priv;
|
|
return 0;
|
|
}
|
|
|
|
void i915_master_destroy(struct drm_device *dev, struct drm_master *master)
|
|
{
|
|
struct drm_i915_master_private *master_priv = master->driver_priv;
|
|
|
|
if (!master_priv)
|
|
return;
|
|
|
|
kfree(master_priv);
|
|
|
|
master->driver_priv = NULL;
|
|
}
|
|
|
|
static void i915_pineview_get_mem_freq(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
u32 tmp;
|
|
|
|
tmp = I915_READ(CLKCFG);
|
|
|
|
switch (tmp & CLKCFG_FSB_MASK) {
|
|
case CLKCFG_FSB_533:
|
|
dev_priv->fsb_freq = 533; /* 133*4 */
|
|
break;
|
|
case CLKCFG_FSB_800:
|
|
dev_priv->fsb_freq = 800; /* 200*4 */
|
|
break;
|
|
case CLKCFG_FSB_667:
|
|
dev_priv->fsb_freq = 667; /* 167*4 */
|
|
break;
|
|
case CLKCFG_FSB_400:
|
|
dev_priv->fsb_freq = 400; /* 100*4 */
|
|
break;
|
|
}
|
|
|
|
switch (tmp & CLKCFG_MEM_MASK) {
|
|
case CLKCFG_MEM_533:
|
|
dev_priv->mem_freq = 533;
|
|
break;
|
|
case CLKCFG_MEM_667:
|
|
dev_priv->mem_freq = 667;
|
|
break;
|
|
case CLKCFG_MEM_800:
|
|
dev_priv->mem_freq = 800;
|
|
break;
|
|
}
|
|
|
|
/* detect pineview DDR3 setting */
|
|
tmp = I915_READ(CSHRDDR3CTL);
|
|
dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
|
|
}
|
|
|
|
static void i915_ironlake_get_mem_freq(struct drm_device *dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
u16 ddrpll, csipll;
|
|
|
|
ddrpll = I915_READ16(DDRMPLL1);
|
|
csipll = I915_READ16(CSIPLL0);
|
|
|
|
switch (ddrpll & 0xff) {
|
|
case 0xc:
|
|
dev_priv->mem_freq = 800;
|
|
break;
|
|
case 0x10:
|
|
dev_priv->mem_freq = 1066;
|
|
break;
|
|
case 0x14:
|
|
dev_priv->mem_freq = 1333;
|
|
break;
|
|
case 0x18:
|
|
dev_priv->mem_freq = 1600;
|
|
break;
|
|
default:
|
|
DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
|
|
ddrpll & 0xff);
|
|
dev_priv->mem_freq = 0;
|
|
break;
|
|
}
|
|
|
|
dev_priv->r_t = dev_priv->mem_freq;
|
|
|
|
switch (csipll & 0x3ff) {
|
|
case 0x00c:
|
|
dev_priv->fsb_freq = 3200;
|
|
break;
|
|
case 0x00e:
|
|
dev_priv->fsb_freq = 3733;
|
|
break;
|
|
case 0x010:
|
|
dev_priv->fsb_freq = 4266;
|
|
break;
|
|
case 0x012:
|
|
dev_priv->fsb_freq = 4800;
|
|
break;
|
|
case 0x014:
|
|
dev_priv->fsb_freq = 5333;
|
|
break;
|
|
case 0x016:
|
|
dev_priv->fsb_freq = 5866;
|
|
break;
|
|
case 0x018:
|
|
dev_priv->fsb_freq = 6400;
|
|
break;
|
|
default:
|
|
DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
|
|
csipll & 0x3ff);
|
|
dev_priv->fsb_freq = 0;
|
|
break;
|
|
}
|
|
|
|
if (dev_priv->fsb_freq == 3200) {
|
|
dev_priv->c_m = 0;
|
|
} else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
|
|
dev_priv->c_m = 1;
|
|
} else {
|
|
dev_priv->c_m = 2;
|
|
}
|
|
}
|
|
|
|
static const struct cparams {
|
|
u16 i;
|
|
u16 t;
|
|
u16 m;
|
|
u16 c;
|
|
} cparams[] = {
|
|
{ 1, 1333, 301, 28664 },
|
|
{ 1, 1066, 294, 24460 },
|
|
{ 1, 800, 294, 25192 },
|
|
{ 0, 1333, 276, 27605 },
|
|
{ 0, 1066, 276, 27605 },
|
|
{ 0, 800, 231, 23784 },
|
|
};
|
|
|
|
unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
|
|
{
|
|
u64 total_count, diff, ret;
|
|
u32 count1, count2, count3, m = 0, c = 0;
|
|
unsigned long now = jiffies_to_msecs(jiffies), diff1;
|
|
int i;
|
|
|
|
diff1 = now - dev_priv->last_time1;
|
|
|
|
count1 = I915_READ(DMIEC);
|
|
count2 = I915_READ(DDREC);
|
|
count3 = I915_READ(CSIEC);
|
|
|
|
total_count = count1 + count2 + count3;
|
|
|
|
/* FIXME: handle per-counter overflow */
|
|
if (total_count < dev_priv->last_count1) {
|
|
diff = ~0UL - dev_priv->last_count1;
|
|
diff += total_count;
|
|
} else {
|
|
diff = total_count - dev_priv->last_count1;
|
|
}
|
|
|
|
for (i = 0; i < ARRAY_SIZE(cparams); i++) {
|
|
if (cparams[i].i == dev_priv->c_m &&
|
|
cparams[i].t == dev_priv->r_t) {
|
|
m = cparams[i].m;
|
|
c = cparams[i].c;
|
|
break;
|
|
}
|
|
}
|
|
|
|
diff = div_u64(diff, diff1);
|
|
ret = ((m * diff) + c);
|
|
ret = div_u64(ret, 10);
|
|
|
|
dev_priv->last_count1 = total_count;
|
|
dev_priv->last_time1 = now;
|
|
|
|
return ret;
|
|
}
|
|
|
|
unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
|
|
{
|
|
unsigned long m, x, b;
|
|
u32 tsfs;
|
|
|
|
tsfs = I915_READ(TSFS);
|
|
|
|
m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
|
|
x = I915_READ8(TR1);
|
|
|
|
b = tsfs & TSFS_INTR_MASK;
|
|
|
|
return ((m * x) / 127) - b;
|
|
}
|
|
|
|
static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
|
|
{
|
|
static const struct v_table {
|
|
u16 vd; /* in .1 mil */
|
|
u16 vm; /* in .1 mil */
|
|
} v_table[] = {
|
|
{ 0, 0, },
|
|
{ 375, 0, },
|
|
{ 500, 0, },
|
|
{ 625, 0, },
|
|
{ 750, 0, },
|
|
{ 875, 0, },
|
|
{ 1000, 0, },
|
|
{ 1125, 0, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4125, 3000, },
|
|
{ 4250, 3125, },
|
|
{ 4375, 3250, },
|
|
{ 4500, 3375, },
|
|
{ 4625, 3500, },
|
|
{ 4750, 3625, },
|
|
{ 4875, 3750, },
|
|
{ 5000, 3875, },
|
|
{ 5125, 4000, },
|
|
{ 5250, 4125, },
|
|
{ 5375, 4250, },
|
|
{ 5500, 4375, },
|
|
{ 5625, 4500, },
|
|
{ 5750, 4625, },
|
|
{ 5875, 4750, },
|
|
{ 6000, 4875, },
|
|
{ 6125, 5000, },
|
|
{ 6250, 5125, },
|
|
{ 6375, 5250, },
|
|
{ 6500, 5375, },
|
|
{ 6625, 5500, },
|
|
{ 6750, 5625, },
|
|
{ 6875, 5750, },
|
|
{ 7000, 5875, },
|
|
{ 7125, 6000, },
|
|
{ 7250, 6125, },
|
|
{ 7375, 6250, },
|
|
{ 7500, 6375, },
|
|
{ 7625, 6500, },
|
|
{ 7750, 6625, },
|
|
{ 7875, 6750, },
|
|
{ 8000, 6875, },
|
|
{ 8125, 7000, },
|
|
{ 8250, 7125, },
|
|
{ 8375, 7250, },
|
|
{ 8500, 7375, },
|
|
{ 8625, 7500, },
|
|
{ 8750, 7625, },
|
|
{ 8875, 7750, },
|
|
{ 9000, 7875, },
|
|
{ 9125, 8000, },
|
|
{ 9250, 8125, },
|
|
{ 9375, 8250, },
|
|
{ 9500, 8375, },
|
|
{ 9625, 8500, },
|
|
{ 9750, 8625, },
|
|
{ 9875, 8750, },
|
|
{ 10000, 8875, },
|
|
{ 10125, 9000, },
|
|
{ 10250, 9125, },
|
|
{ 10375, 9250, },
|
|
{ 10500, 9375, },
|
|
{ 10625, 9500, },
|
|
{ 10750, 9625, },
|
|
{ 10875, 9750, },
|
|
{ 11000, 9875, },
|
|
{ 11125, 10000, },
|
|
{ 11250, 10125, },
|
|
{ 11375, 10250, },
|
|
{ 11500, 10375, },
|
|
{ 11625, 10500, },
|
|
{ 11750, 10625, },
|
|
{ 11875, 10750, },
|
|
{ 12000, 10875, },
|
|
{ 12125, 11000, },
|
|
{ 12250, 11125, },
|
|
{ 12375, 11250, },
|
|
{ 12500, 11375, },
|
|
{ 12625, 11500, },
|
|
{ 12750, 11625, },
|
|
{ 12875, 11750, },
|
|
{ 13000, 11875, },
|
|
{ 13125, 12000, },
|
|
{ 13250, 12125, },
|
|
{ 13375, 12250, },
|
|
{ 13500, 12375, },
|
|
{ 13625, 12500, },
|
|
{ 13750, 12625, },
|
|
{ 13875, 12750, },
|
|
{ 14000, 12875, },
|
|
{ 14125, 13000, },
|
|
{ 14250, 13125, },
|
|
{ 14375, 13250, },
|
|
{ 14500, 13375, },
|
|
{ 14625, 13500, },
|
|
{ 14750, 13625, },
|
|
{ 14875, 13750, },
|
|
{ 15000, 13875, },
|
|
{ 15125, 14000, },
|
|
{ 15250, 14125, },
|
|
{ 15375, 14250, },
|
|
{ 15500, 14375, },
|
|
{ 15625, 14500, },
|
|
{ 15750, 14625, },
|
|
{ 15875, 14750, },
|
|
{ 16000, 14875, },
|
|
{ 16125, 15000, },
|
|
};
|
|
if (dev_priv->info->is_mobile)
|
|
return v_table[pxvid].vm;
|
|
else
|
|
return v_table[pxvid].vd;
|
|
}
|
|
|
|
void i915_update_gfx_val(struct drm_i915_private *dev_priv)
|
|
{
|
|
struct timespec now, diff1;
|
|
u64 diff;
|
|
unsigned long diffms;
|
|
u32 count;
|
|
|
|
getrawmonotonic(&now);
|
|
diff1 = timespec_sub(now, dev_priv->last_time2);
|
|
|
|
/* Don't divide by 0 */
|
|
diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
|
|
if (!diffms)
|
|
return;
|
|
|
|
count = I915_READ(GFXEC);
|
|
|
|
if (count < dev_priv->last_count2) {
|
|
diff = ~0UL - dev_priv->last_count2;
|
|
diff += count;
|
|
} else {
|
|
diff = count - dev_priv->last_count2;
|
|
}
|
|
|
|
dev_priv->last_count2 = count;
|
|
dev_priv->last_time2 = now;
|
|
|
|
/* More magic constants... */
|
|
diff = diff * 1181;
|
|
diff = div_u64(diff, diffms * 10);
|
|
dev_priv->gfx_power = diff;
|
|
}
|
|
|
|
unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
|
|
{
|
|
unsigned long t, corr, state1, corr2, state2;
|
|
u32 pxvid, ext_v;
|
|
|
|
pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->cur_delay * 4));
|
|
pxvid = (pxvid >> 24) & 0x7f;
|
|
ext_v = pvid_to_extvid(dev_priv, pxvid);
|
|
|
|
state1 = ext_v;
|
|
|
|
t = i915_mch_val(dev_priv);
|
|
|
|
/* Revel in the empirically derived constants */
|
|
|
|
/* Correction factor in 1/100000 units */
|
|
if (t > 80)
|
|
corr = ((t * 2349) + 135940);
|
|
else if (t >= 50)
|
|
corr = ((t * 964) + 29317);
|
|
else /* < 50 */
|
|
corr = ((t * 301) + 1004);
|
|
|
|
corr = corr * ((150142 * state1) / 10000 - 78642);
|
|
corr /= 100000;
|
|
corr2 = (corr * dev_priv->corr);
|
|
|
|
state2 = (corr2 * state1) / 10000;
|
|
state2 /= 100; /* convert to mW */
|
|
|
|
i915_update_gfx_val(dev_priv);
|
|
|
|
return dev_priv->gfx_power + state2;
|
|
}
|
|
|
|
/* Global for IPS driver to get at the current i915 device */
|
|
static struct drm_i915_private *i915_mch_dev;
|
|
/*
|
|
* Lock protecting IPS related data structures
|
|
* - i915_mch_dev
|
|
* - dev_priv->max_delay
|
|
* - dev_priv->min_delay
|
|
* - dev_priv->fmax
|
|
* - dev_priv->gpu_busy
|
|
*/
|
|
static DEFINE_SPINLOCK(mchdev_lock);
|
|
|
|
/**
|
|
* i915_read_mch_val - return value for IPS use
|
|
*
|
|
* Calculate and return a value for the IPS driver to use when deciding whether
|
|
* we have thermal and power headroom to increase CPU or GPU power budget.
|
|
*/
|
|
unsigned long i915_read_mch_val(void)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
unsigned long chipset_val, graphics_val, ret = 0;
|
|
|
|
spin_lock(&mchdev_lock);
|
|
if (!i915_mch_dev)
|
|
goto out_unlock;
|
|
dev_priv = i915_mch_dev;
|
|
|
|
chipset_val = i915_chipset_val(dev_priv);
|
|
graphics_val = i915_gfx_val(dev_priv);
|
|
|
|
ret = chipset_val + graphics_val;
|
|
|
|
out_unlock:
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i915_read_mch_val);
|
|
|
|
/**
|
|
* i915_gpu_raise - raise GPU frequency limit
|
|
*
|
|
* Raise the limit; IPS indicates we have thermal headroom.
|
|
*/
|
|
bool i915_gpu_raise(void)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
bool ret = true;
|
|
|
|
spin_lock(&mchdev_lock);
|
|
if (!i915_mch_dev) {
|
|
ret = false;
|
|
goto out_unlock;
|
|
}
|
|
dev_priv = i915_mch_dev;
|
|
|
|
if (dev_priv->max_delay > dev_priv->fmax)
|
|
dev_priv->max_delay--;
|
|
|
|
out_unlock:
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i915_gpu_raise);
|
|
|
|
/**
|
|
* i915_gpu_lower - lower GPU frequency limit
|
|
*
|
|
* IPS indicates we're close to a thermal limit, so throttle back the GPU
|
|
* frequency maximum.
|
|
*/
|
|
bool i915_gpu_lower(void)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
bool ret = true;
|
|
|
|
spin_lock(&mchdev_lock);
|
|
if (!i915_mch_dev) {
|
|
ret = false;
|
|
goto out_unlock;
|
|
}
|
|
dev_priv = i915_mch_dev;
|
|
|
|
if (dev_priv->max_delay < dev_priv->min_delay)
|
|
dev_priv->max_delay++;
|
|
|
|
out_unlock:
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i915_gpu_lower);
|
|
|
|
/**
|
|
* i915_gpu_busy - indicate GPU business to IPS
|
|
*
|
|
* Tell the IPS driver whether or not the GPU is busy.
|
|
*/
|
|
bool i915_gpu_busy(void)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
bool ret = false;
|
|
|
|
spin_lock(&mchdev_lock);
|
|
if (!i915_mch_dev)
|
|
goto out_unlock;
|
|
dev_priv = i915_mch_dev;
|
|
|
|
ret = dev_priv->busy;
|
|
|
|
out_unlock:
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i915_gpu_busy);
|
|
|
|
/**
|
|
* i915_gpu_turbo_disable - disable graphics turbo
|
|
*
|
|
* Disable graphics turbo by resetting the max frequency and setting the
|
|
* current frequency to the default.
|
|
*/
|
|
bool i915_gpu_turbo_disable(void)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
bool ret = true;
|
|
|
|
spin_lock(&mchdev_lock);
|
|
if (!i915_mch_dev) {
|
|
ret = false;
|
|
goto out_unlock;
|
|
}
|
|
dev_priv = i915_mch_dev;
|
|
|
|
dev_priv->max_delay = dev_priv->fstart;
|
|
|
|
if (!ironlake_set_drps(dev_priv->dev, dev_priv->fstart))
|
|
ret = false;
|
|
|
|
out_unlock:
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
|
|
|
|
/**
|
|
* Tells the intel_ips driver that the i915 driver is now loaded, if
|
|
* IPS got loaded first.
|
|
*
|
|
* This awkward dance is so that neither module has to depend on the
|
|
* other in order for IPS to do the appropriate communication of
|
|
* GPU turbo limits to i915.
|
|
*/
|
|
static void
|
|
ips_ping_for_i915_load(void)
|
|
{
|
|
void (*link)(void);
|
|
|
|
link = symbol_get(ips_link_to_i915_driver);
|
|
if (link) {
|
|
link();
|
|
symbol_put(ips_link_to_i915_driver);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* i915_driver_load - setup chip and create an initial config
|
|
* @dev: DRM device
|
|
* @flags: startup flags
|
|
*
|
|
* The driver load routine has to do several things:
|
|
* - drive output discovery via intel_modeset_init()
|
|
* - initialize the memory manager
|
|
* - allocate initial config memory
|
|
* - setup the DRM framebuffer with the allocated memory
|
|
*/
|
|
int i915_driver_load(struct drm_device *dev, unsigned long flags)
|
|
{
|
|
struct drm_i915_private *dev_priv;
|
|
int ret = 0, mmio_bar;
|
|
uint32_t agp_size;
|
|
|
|
/* i915 has 4 more counters */
|
|
dev->counters += 4;
|
|
dev->types[6] = _DRM_STAT_IRQ;
|
|
dev->types[7] = _DRM_STAT_PRIMARY;
|
|
dev->types[8] = _DRM_STAT_SECONDARY;
|
|
dev->types[9] = _DRM_STAT_DMA;
|
|
|
|
dev_priv = kzalloc(sizeof(drm_i915_private_t), GFP_KERNEL);
|
|
if (dev_priv == NULL)
|
|
return -ENOMEM;
|
|
|
|
dev->dev_private = (void *)dev_priv;
|
|
dev_priv->dev = dev;
|
|
dev_priv->info = (struct intel_device_info *) flags;
|
|
|
|
if (i915_get_bridge_dev(dev)) {
|
|
ret = -EIO;
|
|
goto free_priv;
|
|
}
|
|
|
|
/* overlay on gen2 is broken and can't address above 1G */
|
|
if (IS_GEN2(dev))
|
|
dma_set_coherent_mask(&dev->pdev->dev, DMA_BIT_MASK(30));
|
|
|
|
mmio_bar = IS_GEN2(dev) ? 1 : 0;
|
|
dev_priv->regs = pci_iomap(dev->pdev, mmio_bar, 0);
|
|
if (!dev_priv->regs) {
|
|
DRM_ERROR("failed to map registers\n");
|
|
ret = -EIO;
|
|
goto put_bridge;
|
|
}
|
|
|
|
dev_priv->mm.gtt = intel_gtt_get();
|
|
if (!dev_priv->mm.gtt) {
|
|
DRM_ERROR("Failed to initialize GTT\n");
|
|
ret = -ENODEV;
|
|
goto out_iomapfree;
|
|
}
|
|
|
|
agp_size = dev_priv->mm.gtt->gtt_mappable_entries << PAGE_SHIFT;
|
|
|
|
dev_priv->mm.gtt_mapping =
|
|
io_mapping_create_wc(dev->agp->base, agp_size);
|
|
if (dev_priv->mm.gtt_mapping == NULL) {
|
|
ret = -EIO;
|
|
goto out_rmmap;
|
|
}
|
|
|
|
/* Set up a WC MTRR for non-PAT systems. This is more common than
|
|
* one would think, because the kernel disables PAT on first
|
|
* generation Core chips because WC PAT gets overridden by a UC
|
|
* MTRR if present. Even if a UC MTRR isn't present.
|
|
*/
|
|
dev_priv->mm.gtt_mtrr = mtrr_add(dev->agp->base,
|
|
agp_size,
|
|
MTRR_TYPE_WRCOMB, 1);
|
|
if (dev_priv->mm.gtt_mtrr < 0) {
|
|
DRM_INFO("MTRR allocation failed. Graphics "
|
|
"performance may suffer.\n");
|
|
}
|
|
|
|
/* The i915 workqueue is primarily used for batched retirement of
|
|
* requests (and thus managing bo) once the task has been completed
|
|
* by the GPU. i915_gem_retire_requests() is called directly when we
|
|
* need high-priority retirement, such as waiting for an explicit
|
|
* bo.
|
|
*
|
|
* It is also used for periodic low-priority events, such as
|
|
* idle-timers and recording error state.
|
|
*
|
|
* All tasks on the workqueue are expected to acquire the dev mutex
|
|
* so there is no point in running more than one instance of the
|
|
* workqueue at any time: max_active = 1 and NON_REENTRANT.
|
|
*/
|
|
dev_priv->wq = alloc_workqueue("i915",
|
|
WQ_UNBOUND | WQ_NON_REENTRANT,
|
|
1);
|
|
if (dev_priv->wq == NULL) {
|
|
DRM_ERROR("Failed to create our workqueue.\n");
|
|
ret = -ENOMEM;
|
|
goto out_iomapfree;
|
|
}
|
|
|
|
/* enable GEM by default */
|
|
dev_priv->has_gem = 1;
|
|
|
|
dev->driver->get_vblank_counter = i915_get_vblank_counter;
|
|
dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
|
|
if (IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) {
|
|
dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
|
|
dev->driver->get_vblank_counter = gm45_get_vblank_counter;
|
|
}
|
|
|
|
/* Try to make sure MCHBAR is enabled before poking at it */
|
|
intel_setup_mchbar(dev);
|
|
intel_setup_gmbus(dev);
|
|
intel_opregion_setup(dev);
|
|
|
|
/* Make sure the bios did its job and set up vital registers */
|
|
intel_setup_bios(dev);
|
|
|
|
i915_gem_load(dev);
|
|
|
|
/* Init HWS */
|
|
if (!I915_NEED_GFX_HWS(dev)) {
|
|
ret = i915_init_phys_hws(dev);
|
|
if (ret)
|
|
goto out_gem_unload;
|
|
}
|
|
|
|
if (IS_PINEVIEW(dev))
|
|
i915_pineview_get_mem_freq(dev);
|
|
else if (IS_GEN5(dev))
|
|
i915_ironlake_get_mem_freq(dev);
|
|
|
|
/* On the 945G/GM, the chipset reports the MSI capability on the
|
|
* integrated graphics even though the support isn't actually there
|
|
* according to the published specs. It doesn't appear to function
|
|
* correctly in testing on 945G.
|
|
* This may be a side effect of MSI having been made available for PEG
|
|
* and the registers being closely associated.
|
|
*
|
|
* According to chipset errata, on the 965GM, MSI interrupts may
|
|
* be lost or delayed, but we use them anyways to avoid
|
|
* stuck interrupts on some machines.
|
|
*/
|
|
if (!IS_I945G(dev) && !IS_I945GM(dev))
|
|
pci_enable_msi(dev->pdev);
|
|
|
|
spin_lock_init(&dev_priv->irq_lock);
|
|
spin_lock_init(&dev_priv->error_lock);
|
|
dev_priv->trace_irq_seqno = 0;
|
|
|
|
ret = drm_vblank_init(dev, I915_NUM_PIPE);
|
|
if (ret)
|
|
goto out_gem_unload;
|
|
|
|
/* Start out suspended */
|
|
dev_priv->mm.suspended = 1;
|
|
|
|
intel_detect_pch(dev);
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
ret = i915_load_modeset_init(dev);
|
|
if (ret < 0) {
|
|
DRM_ERROR("failed to init modeset\n");
|
|
goto out_gem_unload;
|
|
}
|
|
}
|
|
|
|
/* Must be done after probing outputs */
|
|
intel_opregion_init(dev);
|
|
acpi_video_register();
|
|
|
|
setup_timer(&dev_priv->hangcheck_timer, i915_hangcheck_elapsed,
|
|
(unsigned long) dev);
|
|
|
|
spin_lock(&mchdev_lock);
|
|
i915_mch_dev = dev_priv;
|
|
dev_priv->mchdev_lock = &mchdev_lock;
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
ips_ping_for_i915_load();
|
|
|
|
return 0;
|
|
|
|
out_gem_unload:
|
|
if (dev->pdev->msi_enabled)
|
|
pci_disable_msi(dev->pdev);
|
|
|
|
intel_teardown_gmbus(dev);
|
|
intel_teardown_mchbar(dev);
|
|
destroy_workqueue(dev_priv->wq);
|
|
out_iomapfree:
|
|
io_mapping_free(dev_priv->mm.gtt_mapping);
|
|
out_rmmap:
|
|
pci_iounmap(dev->pdev, dev_priv->regs);
|
|
put_bridge:
|
|
pci_dev_put(dev_priv->bridge_dev);
|
|
free_priv:
|
|
kfree(dev_priv);
|
|
return ret;
|
|
}
|
|
|
|
int i915_driver_unload(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
int ret;
|
|
|
|
spin_lock(&mchdev_lock);
|
|
i915_mch_dev = NULL;
|
|
spin_unlock(&mchdev_lock);
|
|
|
|
if (dev_priv->mm.inactive_shrinker.shrink)
|
|
unregister_shrinker(&dev_priv->mm.inactive_shrinker);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
ret = i915_gpu_idle(dev);
|
|
if (ret)
|
|
DRM_ERROR("failed to idle hardware: %d\n", ret);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
/* Cancel the retire work handler, which should be idle now. */
|
|
cancel_delayed_work_sync(&dev_priv->mm.retire_work);
|
|
|
|
io_mapping_free(dev_priv->mm.gtt_mapping);
|
|
if (dev_priv->mm.gtt_mtrr >= 0) {
|
|
mtrr_del(dev_priv->mm.gtt_mtrr, dev->agp->base,
|
|
dev->agp->agp_info.aper_size * 1024 * 1024);
|
|
dev_priv->mm.gtt_mtrr = -1;
|
|
}
|
|
|
|
acpi_video_unregister();
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
intel_fbdev_fini(dev);
|
|
intel_modeset_cleanup(dev);
|
|
|
|
/*
|
|
* free the memory space allocated for the child device
|
|
* config parsed from VBT
|
|
*/
|
|
if (dev_priv->child_dev && dev_priv->child_dev_num) {
|
|
kfree(dev_priv->child_dev);
|
|
dev_priv->child_dev = NULL;
|
|
dev_priv->child_dev_num = 0;
|
|
}
|
|
|
|
vga_switcheroo_unregister_client(dev->pdev);
|
|
vga_client_register(dev->pdev, NULL, NULL, NULL);
|
|
}
|
|
|
|
/* Free error state after interrupts are fully disabled. */
|
|
del_timer_sync(&dev_priv->hangcheck_timer);
|
|
cancel_work_sync(&dev_priv->error_work);
|
|
i915_destroy_error_state(dev);
|
|
|
|
if (dev->pdev->msi_enabled)
|
|
pci_disable_msi(dev->pdev);
|
|
|
|
intel_opregion_fini(dev);
|
|
|
|
if (drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
/* Flush any outstanding unpin_work. */
|
|
flush_workqueue(dev_priv->wq);
|
|
|
|
i915_gem_free_all_phys_object(dev);
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
i915_gem_cleanup_ringbuffer(dev);
|
|
mutex_unlock(&dev->struct_mutex);
|
|
if (I915_HAS_FBC(dev) && i915_powersave)
|
|
i915_cleanup_compression(dev);
|
|
drm_mm_takedown(&dev_priv->mm.stolen);
|
|
|
|
intel_cleanup_overlay(dev);
|
|
|
|
if (!I915_NEED_GFX_HWS(dev))
|
|
i915_free_hws(dev);
|
|
}
|
|
|
|
if (dev_priv->regs != NULL)
|
|
pci_iounmap(dev->pdev, dev_priv->regs);
|
|
|
|
intel_teardown_gmbus(dev);
|
|
intel_teardown_mchbar(dev);
|
|
|
|
destroy_workqueue(dev_priv->wq);
|
|
|
|
pci_dev_put(dev_priv->bridge_dev);
|
|
kfree(dev->dev_private);
|
|
|
|
return 0;
|
|
}
|
|
|
|
int i915_driver_open(struct drm_device *dev, struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv;
|
|
|
|
DRM_DEBUG_DRIVER("\n");
|
|
file_priv = kmalloc(sizeof(*file_priv), GFP_KERNEL);
|
|
if (!file_priv)
|
|
return -ENOMEM;
|
|
|
|
file->driver_priv = file_priv;
|
|
|
|
spin_lock_init(&file_priv->mm.lock);
|
|
INIT_LIST_HEAD(&file_priv->mm.request_list);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* i915_driver_lastclose - clean up after all DRM clients have exited
|
|
* @dev: DRM device
|
|
*
|
|
* Take care of cleaning up after all DRM clients have exited. In the
|
|
* mode setting case, we want to restore the kernel's initial mode (just
|
|
* in case the last client left us in a bad state).
|
|
*
|
|
* Additionally, in the non-mode setting case, we'll tear down the AGP
|
|
* and DMA structures, since the kernel won't be using them, and clea
|
|
* up any GEM state.
|
|
*/
|
|
void i915_driver_lastclose(struct drm_device * dev)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
|
|
if (!dev_priv || drm_core_check_feature(dev, DRIVER_MODESET)) {
|
|
drm_fb_helper_restore();
|
|
vga_switcheroo_process_delayed_switch();
|
|
return;
|
|
}
|
|
|
|
i915_gem_lastclose(dev);
|
|
|
|
if (dev_priv->agp_heap)
|
|
i915_mem_takedown(&(dev_priv->agp_heap));
|
|
|
|
i915_dma_cleanup(dev);
|
|
}
|
|
|
|
void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
|
|
{
|
|
drm_i915_private_t *dev_priv = dev->dev_private;
|
|
i915_gem_release(dev, file_priv);
|
|
if (!drm_core_check_feature(dev, DRIVER_MODESET))
|
|
i915_mem_release(dev, file_priv, dev_priv->agp_heap);
|
|
}
|
|
|
|
void i915_driver_postclose(struct drm_device *dev, struct drm_file *file)
|
|
{
|
|
struct drm_i915_file_private *file_priv = file->driver_priv;
|
|
|
|
kfree(file_priv);
|
|
}
|
|
|
|
struct drm_ioctl_desc i915_ioctls[] = {
|
|
DRM_IOCTL_DEF_DRV(I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_FLIP, i915_flip_bufs, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_GETPARAM, i915_getparam, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(I915_ALLOC, i915_mem_alloc, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_FREE, i915_mem_free, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
|
|
DRM_IOCTL_DEF_DRV(I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_EXECBUFFER2, i915_gem_execbuffer2, DRM_AUTH|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_CREATE, i915_gem_create_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_PREAD, i915_gem_pread_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_PWRITE, i915_gem_pwrite_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP, i915_gem_mmap_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_MMAP_GTT, i915_gem_mmap_gtt_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_SET_TILING, i915_gem_set_tiling, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_GET_TILING, i915_gem_get_tiling, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_GET_APERTURE, i915_gem_get_aperture_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GET_PIPE_FROM_CRTC_ID, intel_get_pipe_from_crtc_id, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_GEM_MADVISE, i915_gem_madvise_ioctl, DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_OVERLAY_PUT_IMAGE, intel_overlay_put_image, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
|
|
DRM_IOCTL_DEF_DRV(I915_OVERLAY_ATTRS, intel_overlay_attrs, DRM_MASTER|DRM_CONTROL_ALLOW|DRM_UNLOCKED),
|
|
};
|
|
|
|
int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
|
|
|
|
/**
|
|
* Determine if the device really is AGP or not.
|
|
*
|
|
* All Intel graphics chipsets are treated as AGP, even if they are really
|
|
* PCI-e.
|
|
*
|
|
* \param dev The device to be tested.
|
|
*
|
|
* \returns
|
|
* A value of 1 is always retured to indictate every i9x5 is AGP.
|
|
*/
|
|
int i915_driver_device_is_agp(struct drm_device * dev)
|
|
{
|
|
return 1;
|
|
}
|