mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-28 11:18:45 +07:00
287 lines
7.4 KiB
C
287 lines
7.4 KiB
C
/*
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* Copyright 2018 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include "base.h"
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#include <nvif/cl507c.h>
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#include <nvif/event.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "nouveau_bo.h"
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void
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base507c_update(struct nv50_wndw *wndw, u32 *interlock)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 2))) {
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evo_mthd(push, 0x0080, 1);
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evo_data(push, interlock[NV50_DISP_INTERLOCK_CORE]);
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evo_kick(push, &wndw->wndw);
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}
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}
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void
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base507c_image_clr(struct nv50_wndw *wndw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 4))) {
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evo_mthd(push, 0x0084, 1);
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evo_data(push, 0x00000000);
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evo_mthd(push, 0x00c0, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, &wndw->wndw);
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}
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}
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static void
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base507c_image_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 10))) {
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evo_mthd(push, 0x0084, 1);
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evo_data(push, asyw->image.mode << 8 |
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asyw->image.interval << 4);
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evo_mthd(push, 0x00c0, 1);
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evo_data(push, asyw->image.handle[0]);
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evo_mthd(push, 0x0800, 5);
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evo_data(push, asyw->image.offset[0] >> 8);
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evo_data(push, 0x00000000);
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evo_data(push, asyw->image.h << 16 | asyw->image.w);
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evo_data(push, asyw->image.layout << 20 |
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(asyw->image.pitch[0] >> 8) << 8 |
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asyw->image.blocks[0] << 8 |
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asyw->image.blockh);
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evo_data(push, asyw->image.kind << 16 |
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asyw->image.format << 8);
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evo_kick(push, &wndw->wndw);
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}
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}
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void
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base507c_xlut_clr(struct nv50_wndw *wndw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 2))) {
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evo_mthd(push, 0x00e0, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, &wndw->wndw);
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}
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}
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void
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base507c_xlut_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 2))) {
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evo_mthd(push, 0x00e0, 1);
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evo_data(push, 0x40000000);
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evo_kick(push, &wndw->wndw);
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}
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}
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int
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base507c_ntfy_wait_begun(struct nouveau_bo *bo, u32 offset,
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struct nvif_device *device)
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{
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s64 time = nvif_msec(device, 2000ULL,
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u32 data = nouveau_bo_rd32(bo, offset / 4);
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if ((data & 0xc0000000) == 0x40000000)
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break;
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usleep_range(1, 2);
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);
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return time < 0 ? time : 0;
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}
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void
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base507c_ntfy_clr(struct nv50_wndw *wndw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 2))) {
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evo_mthd(push, 0x00a4, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, &wndw->wndw);
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}
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}
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void
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base507c_ntfy_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 3))) {
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evo_mthd(push, 0x00a0, 2);
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evo_data(push, asyw->ntfy.awaken << 30 | asyw->ntfy.offset);
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evo_data(push, asyw->ntfy.handle);
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evo_kick(push, &wndw->wndw);
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}
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}
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void
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base507c_ntfy_reset(struct nouveau_bo *bo, u32 offset)
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{
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nouveau_bo_wr32(bo, offset / 4, 0x00000000);
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}
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void
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base507c_sema_clr(struct nv50_wndw *wndw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 2))) {
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evo_mthd(push, 0x0094, 1);
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evo_data(push, 0x00000000);
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evo_kick(push, &wndw->wndw);
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}
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}
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void
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base507c_sema_set(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw)
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{
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u32 *push;
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if ((push = evo_wait(&wndw->wndw, 5))) {
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evo_mthd(push, 0x0088, 4);
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evo_data(push, asyw->sema.offset);
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evo_data(push, asyw->sema.acquire);
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evo_data(push, asyw->sema.release);
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evo_data(push, asyw->sema.handle);
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evo_kick(push, &wndw->wndw);
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}
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}
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void
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base507c_release(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
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struct nv50_head_atom *asyh)
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{
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asyh->base.cpp = 0;
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}
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int
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base507c_acquire(struct nv50_wndw *wndw, struct nv50_wndw_atom *asyw,
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struct nv50_head_atom *asyh)
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{
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const struct drm_framebuffer *fb = asyw->state.fb;
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int ret;
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if (!fb->format->depth)
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return -EINVAL;
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ret = drm_atomic_helper_check_plane_state(&asyw->state, &asyh->state,
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DRM_PLANE_HELPER_NO_SCALING,
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DRM_PLANE_HELPER_NO_SCALING,
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false, true);
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if (ret)
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return ret;
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if (!wndw->func->ilut) {
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if ((asyh->base.cpp != 1) ^ (fb->format->cpp[0] != 1))
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asyh->state.color_mgmt_changed = true;
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}
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asyh->base.depth = fb->format->depth;
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asyh->base.cpp = fb->format->cpp[0];
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asyh->base.x = asyw->state.src.x1 >> 16;
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asyh->base.y = asyw->state.src.y1 >> 16;
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asyh->base.w = asyw->state.fb->width;
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asyh->base.h = asyw->state.fb->height;
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return 0;
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}
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const u32
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base507c_format[] = {
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DRM_FORMAT_C8,
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DRM_FORMAT_RGB565,
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DRM_FORMAT_XRGB1555,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_XRGB8888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_XBGR2101010,
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DRM_FORMAT_ABGR2101010,
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DRM_FORMAT_XBGR8888,
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DRM_FORMAT_ABGR8888,
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0
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};
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static const struct nv50_wndw_func
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base507c = {
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.acquire = base507c_acquire,
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.release = base507c_release,
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.sema_set = base507c_sema_set,
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.sema_clr = base507c_sema_clr,
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.ntfy_reset = base507c_ntfy_reset,
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.ntfy_set = base507c_ntfy_set,
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.ntfy_clr = base507c_ntfy_clr,
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.ntfy_wait_begun = base507c_ntfy_wait_begun,
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.olut_core = 1,
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.xlut_set = base507c_xlut_set,
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.xlut_clr = base507c_xlut_clr,
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.image_set = base507c_image_set,
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.image_clr = base507c_image_clr,
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.update = base507c_update,
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};
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int
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base507c_new_(const struct nv50_wndw_func *func, const u32 *format,
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struct nouveau_drm *drm, int head, s32 oclass, u32 interlock_data,
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struct nv50_wndw **pwndw)
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{
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struct nv50_disp_base_channel_dma_v0 args = {
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.head = head,
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};
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struct nv50_disp *disp = nv50_disp(drm->dev);
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struct nv50_wndw *wndw;
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int ret;
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ret = nv50_wndw_new_(func, drm->dev, DRM_PLANE_TYPE_PRIMARY,
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"base", head, format, BIT(head),
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NV50_DISP_INTERLOCK_BASE, interlock_data, &wndw);
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if (*pwndw = wndw, ret)
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return ret;
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ret = nv50_dmac_create(&drm->client.device, &disp->disp->object,
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&oclass, head, &args, sizeof(args),
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disp->sync->bo.offset, &wndw->wndw);
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if (ret) {
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NV_ERROR(drm, "base%04x allocation failed: %d\n", oclass, ret);
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return ret;
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}
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ret = nvif_notify_init(&wndw->wndw.base.user, wndw->notify.func,
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false, NV50_DISP_BASE_CHANNEL_DMA_V0_NTFY_UEVENT,
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&(struct nvif_notify_uevent_req) {},
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sizeof(struct nvif_notify_uevent_req),
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sizeof(struct nvif_notify_uevent_rep),
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&wndw->notify);
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if (ret)
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return ret;
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wndw->ntfy = NV50_DISP_BASE_NTFY(wndw->id);
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wndw->sema = NV50_DISP_BASE_SEM0(wndw->id);
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wndw->data = 0x00000000;
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return 0;
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}
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int
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base507c_new(struct nouveau_drm *drm, int head, s32 oclass,
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struct nv50_wndw **pwndw)
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{
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return base507c_new_(&base507c, base507c_format, drm, head, oclass,
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0x00000002 << (head * 8), pwndw);
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}
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