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754c73cf4d
The proper spelling of Anniedale SoC with 'e' in the middle. Fix typo in the comment line in intel-family.h header. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Cc: Dave Hansen <dave.hansen@linux.intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Link: http://lkml.kernel.org/r/20170102092229.87036-1-andriy.shevchenko@linux.intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
70 lines
2.2 KiB
C
70 lines
2.2 KiB
C
#ifndef _ASM_X86_INTEL_FAMILY_H
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#define _ASM_X86_INTEL_FAMILY_H
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/*
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* "Big Core" Processors (Branded as Core, Xeon, etc...)
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*
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* The "_X" parts are generally the EP and EX Xeons, or the
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* "Extreme" ones, like Broadwell-E.
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*
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* Things ending in "2" are usually because we have no better
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* name for them. There's no processor called "SILVERMONT2".
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*/
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#define INTEL_FAM6_CORE_YONAH 0x0E
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#define INTEL_FAM6_CORE2_MEROM 0x0F
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#define INTEL_FAM6_CORE2_MEROM_L 0x16
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#define INTEL_FAM6_CORE2_PENRYN 0x17
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#define INTEL_FAM6_CORE2_DUNNINGTON 0x1D
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#define INTEL_FAM6_NEHALEM 0x1E
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#define INTEL_FAM6_NEHALEM_G 0x1F /* Auburndale / Havendale */
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#define INTEL_FAM6_NEHALEM_EP 0x1A
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#define INTEL_FAM6_NEHALEM_EX 0x2E
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#define INTEL_FAM6_WESTMERE 0x25
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#define INTEL_FAM6_WESTMERE_EP 0x2C
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#define INTEL_FAM6_WESTMERE_EX 0x2F
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#define INTEL_FAM6_SANDYBRIDGE 0x2A
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#define INTEL_FAM6_SANDYBRIDGE_X 0x2D
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#define INTEL_FAM6_IVYBRIDGE 0x3A
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#define INTEL_FAM6_IVYBRIDGE_X 0x3E
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#define INTEL_FAM6_HASWELL_CORE 0x3C
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#define INTEL_FAM6_HASWELL_X 0x3F
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#define INTEL_FAM6_HASWELL_ULT 0x45
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#define INTEL_FAM6_HASWELL_GT3E 0x46
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#define INTEL_FAM6_BROADWELL_CORE 0x3D
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#define INTEL_FAM6_BROADWELL_XEON_D 0x56
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#define INTEL_FAM6_BROADWELL_GT3E 0x47
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#define INTEL_FAM6_BROADWELL_X 0x4F
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#define INTEL_FAM6_SKYLAKE_MOBILE 0x4E
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#define INTEL_FAM6_SKYLAKE_DESKTOP 0x5E
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#define INTEL_FAM6_SKYLAKE_X 0x55
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#define INTEL_FAM6_KABYLAKE_MOBILE 0x8E
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#define INTEL_FAM6_KABYLAKE_DESKTOP 0x9E
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/* "Small Core" Processors (Atom) */
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#define INTEL_FAM6_ATOM_PINEVIEW 0x1C
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#define INTEL_FAM6_ATOM_LINCROFT 0x26
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#define INTEL_FAM6_ATOM_PENWELL 0x27
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#define INTEL_FAM6_ATOM_CLOVERVIEW 0x35
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#define INTEL_FAM6_ATOM_CEDARVIEW 0x36
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#define INTEL_FAM6_ATOM_SILVERMONT1 0x37 /* BayTrail/BYT / Valleyview */
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#define INTEL_FAM6_ATOM_SILVERMONT2 0x4D /* Avaton/Rangely */
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#define INTEL_FAM6_ATOM_AIRMONT 0x4C /* CherryTrail / Braswell */
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#define INTEL_FAM6_ATOM_MERRIFIELD 0x4A /* Tangier */
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#define INTEL_FAM6_ATOM_MOOREFIELD 0x5A /* Anniedale */
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#define INTEL_FAM6_ATOM_GOLDMONT 0x5C
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#define INTEL_FAM6_ATOM_DENVERTON 0x5F /* Goldmont Microserver */
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/* Xeon Phi */
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#define INTEL_FAM6_XEON_PHI_KNL 0x57 /* Knights Landing */
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#define INTEL_FAM6_XEON_PHI_KNM 0x85 /* Knights Mill */
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#endif /* _ASM_X86_INTEL_FAMILY_H */
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