mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 23:26:39 +07:00
e0e492e99b
Add Intel AVX(Advanced Vector Extensions) instruction set support to x86 instruction decoder. This adds insn.vex_prefix field for storing VEX prefixes, and introduces some original tags for expressing opcodes attributes. Signed-off-by: Masami Hiramatsu <mhiramat@redhat.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Jim Keniston <jkenisto@us.ibm.com> Cc: Ananth N Mavinakayanahalli <ananth@in.ibm.com> Cc: Christoph Hellwig <hch@infradead.org> Cc: Frank Ch. Eigler <fche@redhat.com> Cc: Frederic Weisbecker <fweisbec@gmail.com> Cc: Jason Baron <jbaron@redhat.com> Cc: K.Prasad <prasad@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Srikar Dronamraju <srikar@linux.vnet.ibm.com> LKML-Reference: <20091027204226.30545.23451.stgit@harusame> Signed-off-by: Ingo Molnar <mingo@elte.hu>
517 lines
13 KiB
C
517 lines
13 KiB
C
/*
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* x86 instruction analysis
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* Copyright (C) IBM Corporation, 2002, 2004, 2009
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*/
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#include <linux/string.h>
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#include <asm/inat.h>
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#include <asm/insn.h>
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#define get_next(t, insn) \
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({t r; r = *(t*)insn->next_byte; insn->next_byte += sizeof(t); r; })
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#define peek_next(t, insn) \
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({t r; r = *(t*)insn->next_byte; r; })
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#define peek_nbyte_next(t, insn, n) \
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({t r; r = *(t*)((insn)->next_byte + n); r; })
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/**
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* insn_init() - initialize struct insn
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* @insn: &struct insn to be initialized
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* @kaddr: address (in kernel memory) of instruction (or copy thereof)
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* @x86_64: !0 for 64-bit kernel or 64-bit app
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*/
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void insn_init(struct insn *insn, const void *kaddr, int x86_64)
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{
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memset(insn, 0, sizeof(*insn));
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insn->kaddr = kaddr;
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insn->next_byte = kaddr;
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insn->x86_64 = x86_64 ? 1 : 0;
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insn->opnd_bytes = 4;
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if (x86_64)
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insn->addr_bytes = 8;
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else
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insn->addr_bytes = 4;
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}
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/**
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* insn_get_prefixes - scan x86 instruction prefix bytes
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* @insn: &struct insn containing instruction
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*
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* Populates the @insn->prefixes bitmap, and updates @insn->next_byte
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* to point to the (first) opcode. No effect if @insn->prefixes.got
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* is already set.
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*/
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void insn_get_prefixes(struct insn *insn)
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{
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struct insn_field *prefixes = &insn->prefixes;
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insn_attr_t attr;
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insn_byte_t b, lb;
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int i, nb;
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if (prefixes->got)
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return;
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nb = 0;
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lb = 0;
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b = peek_next(insn_byte_t, insn);
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attr = inat_get_opcode_attribute(b);
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while (inat_is_legacy_prefix(attr)) {
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/* Skip if same prefix */
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for (i = 0; i < nb; i++)
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if (prefixes->bytes[i] == b)
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goto found;
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if (nb == 4)
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/* Invalid instruction */
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break;
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prefixes->bytes[nb++] = b;
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if (inat_is_address_size_prefix(attr)) {
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/* address size switches 2/4 or 4/8 */
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if (insn->x86_64)
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insn->addr_bytes ^= 12;
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else
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insn->addr_bytes ^= 6;
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} else if (inat_is_operand_size_prefix(attr)) {
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/* oprand size switches 2/4 */
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insn->opnd_bytes ^= 6;
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}
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found:
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prefixes->nbytes++;
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insn->next_byte++;
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lb = b;
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b = peek_next(insn_byte_t, insn);
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attr = inat_get_opcode_attribute(b);
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}
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/* Set the last prefix */
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if (lb && lb != insn->prefixes.bytes[3]) {
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if (unlikely(insn->prefixes.bytes[3])) {
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/* Swap the last prefix */
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b = insn->prefixes.bytes[3];
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for (i = 0; i < nb; i++)
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if (prefixes->bytes[i] == lb)
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prefixes->bytes[i] = b;
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}
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insn->prefixes.bytes[3] = lb;
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}
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/* Decode REX prefix */
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if (insn->x86_64) {
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b = peek_next(insn_byte_t, insn);
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attr = inat_get_opcode_attribute(b);
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if (inat_is_rex_prefix(attr)) {
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insn->rex_prefix.value = b;
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insn->rex_prefix.nbytes = 1;
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insn->next_byte++;
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if (X86_REX_W(b))
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/* REX.W overrides opnd_size */
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insn->opnd_bytes = 8;
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}
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}
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insn->rex_prefix.got = 1;
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/* Decode VEX prefix */
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b = peek_next(insn_byte_t, insn);
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attr = inat_get_opcode_attribute(b);
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if (inat_is_vex_prefix(attr)) {
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insn_byte_t b2 = peek_nbyte_next(insn_byte_t, insn, 1);
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if (!insn->x86_64) {
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/*
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* In 32-bits mode, if the [7:6] bits (mod bits of
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* ModRM) on the second byte are not 11b, it is
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* LDS or LES.
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*/
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if (X86_MODRM_MOD(b2) != 3)
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goto vex_end;
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}
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insn->vex_prefix.bytes[0] = b;
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insn->vex_prefix.bytes[1] = b2;
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if (inat_is_vex3_prefix(attr)) {
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b2 = peek_nbyte_next(insn_byte_t, insn, 2);
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insn->vex_prefix.bytes[2] = b2;
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insn->vex_prefix.nbytes = 3;
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insn->next_byte += 3;
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if (insn->x86_64 && X86_VEX_W(b2))
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/* VEX.W overrides opnd_size */
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insn->opnd_bytes = 8;
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} else {
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insn->vex_prefix.nbytes = 2;
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insn->next_byte += 2;
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}
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}
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vex_end:
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insn->vex_prefix.got = 1;
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prefixes->got = 1;
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return;
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}
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/**
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* insn_get_opcode - collect opcode(s)
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* @insn: &struct insn containing instruction
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*
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* Populates @insn->opcode, updates @insn->next_byte to point past the
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* opcode byte(s), and set @insn->attr (except for groups).
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* If necessary, first collects any preceding (prefix) bytes.
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* Sets @insn->opcode.value = opcode1. No effect if @insn->opcode.got
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* is already 1.
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*/
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void insn_get_opcode(struct insn *insn)
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{
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struct insn_field *opcode = &insn->opcode;
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insn_byte_t op, pfx;
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if (opcode->got)
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return;
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if (!insn->prefixes.got)
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insn_get_prefixes(insn);
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/* Get first opcode */
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op = get_next(insn_byte_t, insn);
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opcode->bytes[0] = op;
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opcode->nbytes = 1;
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/* Check if there is VEX prefix or not */
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if (insn_is_avx(insn)) {
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insn_byte_t m, p;
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m = insn_vex_m_bits(insn);
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p = insn_vex_p_bits(insn);
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insn->attr = inat_get_avx_attribute(op, m, p);
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if (!inat_accept_vex(insn->attr))
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insn->attr = 0; /* This instruction is bad */
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goto end; /* VEX has only 1 byte for opcode */
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}
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insn->attr = inat_get_opcode_attribute(op);
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while (inat_is_escape(insn->attr)) {
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/* Get escaped opcode */
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op = get_next(insn_byte_t, insn);
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opcode->bytes[opcode->nbytes++] = op;
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pfx = insn_last_prefix(insn);
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insn->attr = inat_get_escape_attribute(op, pfx, insn->attr);
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}
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if (inat_must_vex(insn->attr))
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insn->attr = 0; /* This instruction is bad */
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end:
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opcode->got = 1;
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}
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/**
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* insn_get_modrm - collect ModRM byte, if any
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* @insn: &struct insn containing instruction
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*
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* Populates @insn->modrm and updates @insn->next_byte to point past the
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* ModRM byte, if any. If necessary, first collects the preceding bytes
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* (prefixes and opcode(s)). No effect if @insn->modrm.got is already 1.
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*/
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void insn_get_modrm(struct insn *insn)
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{
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struct insn_field *modrm = &insn->modrm;
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insn_byte_t pfx, mod;
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if (modrm->got)
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return;
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if (!insn->opcode.got)
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insn_get_opcode(insn);
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if (inat_has_modrm(insn->attr)) {
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mod = get_next(insn_byte_t, insn);
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modrm->value = mod;
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modrm->nbytes = 1;
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if (inat_is_group(insn->attr)) {
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pfx = insn_last_prefix(insn);
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insn->attr = inat_get_group_attribute(mod, pfx,
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insn->attr);
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}
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}
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if (insn->x86_64 && inat_is_force64(insn->attr))
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insn->opnd_bytes = 8;
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modrm->got = 1;
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}
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/**
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* insn_rip_relative() - Does instruction use RIP-relative addressing mode?
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* @insn: &struct insn containing instruction
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*
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* If necessary, first collects the instruction up to and including the
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* ModRM byte. No effect if @insn->x86_64 is 0.
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*/
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int insn_rip_relative(struct insn *insn)
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{
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struct insn_field *modrm = &insn->modrm;
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if (!insn->x86_64)
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return 0;
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if (!modrm->got)
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insn_get_modrm(insn);
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/*
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* For rip-relative instructions, the mod field (top 2 bits)
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* is zero and the r/m field (bottom 3 bits) is 0x5.
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*/
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return (modrm->nbytes && (modrm->value & 0xc7) == 0x5);
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}
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/**
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* insn_get_sib() - Get the SIB byte of instruction
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* @insn: &struct insn containing instruction
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*
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* If necessary, first collects the instruction up to and including the
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* ModRM byte.
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*/
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void insn_get_sib(struct insn *insn)
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{
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insn_byte_t modrm;
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if (insn->sib.got)
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return;
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if (!insn->modrm.got)
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insn_get_modrm(insn);
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if (insn->modrm.nbytes) {
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modrm = (insn_byte_t)insn->modrm.value;
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if (insn->addr_bytes != 2 &&
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X86_MODRM_MOD(modrm) != 3 && X86_MODRM_RM(modrm) == 4) {
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insn->sib.value = get_next(insn_byte_t, insn);
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insn->sib.nbytes = 1;
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}
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}
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insn->sib.got = 1;
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}
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/**
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* insn_get_displacement() - Get the displacement of instruction
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* @insn: &struct insn containing instruction
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*
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* If necessary, first collects the instruction up to and including the
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* SIB byte.
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* Displacement value is sign-expanded.
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*/
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void insn_get_displacement(struct insn *insn)
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{
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insn_byte_t mod, rm, base;
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if (insn->displacement.got)
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return;
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if (!insn->sib.got)
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insn_get_sib(insn);
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if (insn->modrm.nbytes) {
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/*
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* Interpreting the modrm byte:
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* mod = 00 - no displacement fields (exceptions below)
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* mod = 01 - 1-byte displacement field
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* mod = 10 - displacement field is 4 bytes, or 2 bytes if
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* address size = 2 (0x67 prefix in 32-bit mode)
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* mod = 11 - no memory operand
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*
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* If address size = 2...
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* mod = 00, r/m = 110 - displacement field is 2 bytes
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*
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* If address size != 2...
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* mod != 11, r/m = 100 - SIB byte exists
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* mod = 00, SIB base = 101 - displacement field is 4 bytes
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* mod = 00, r/m = 101 - rip-relative addressing, displacement
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* field is 4 bytes
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*/
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mod = X86_MODRM_MOD(insn->modrm.value);
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rm = X86_MODRM_RM(insn->modrm.value);
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base = X86_SIB_BASE(insn->sib.value);
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if (mod == 3)
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goto out;
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if (mod == 1) {
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insn->displacement.value = get_next(char, insn);
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insn->displacement.nbytes = 1;
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} else if (insn->addr_bytes == 2) {
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if ((mod == 0 && rm == 6) || mod == 2) {
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insn->displacement.value =
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get_next(short, insn);
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insn->displacement.nbytes = 2;
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}
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} else {
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if ((mod == 0 && rm == 5) || mod == 2 ||
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(mod == 0 && base == 5)) {
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insn->displacement.value = get_next(int, insn);
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insn->displacement.nbytes = 4;
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}
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}
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}
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out:
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insn->displacement.got = 1;
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}
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/* Decode moffset16/32/64 */
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static void __get_moffset(struct insn *insn)
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{
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switch (insn->addr_bytes) {
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case 2:
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insn->moffset1.value = get_next(short, insn);
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insn->moffset1.nbytes = 2;
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break;
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case 4:
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insn->moffset1.value = get_next(int, insn);
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insn->moffset1.nbytes = 4;
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break;
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case 8:
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insn->moffset1.value = get_next(int, insn);
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insn->moffset1.nbytes = 4;
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insn->moffset2.value = get_next(int, insn);
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insn->moffset2.nbytes = 4;
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break;
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}
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insn->moffset1.got = insn->moffset2.got = 1;
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}
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/* Decode imm v32(Iz) */
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static void __get_immv32(struct insn *insn)
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{
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switch (insn->opnd_bytes) {
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case 2:
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insn->immediate.value = get_next(short, insn);
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insn->immediate.nbytes = 2;
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break;
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case 4:
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case 8:
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insn->immediate.value = get_next(int, insn);
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insn->immediate.nbytes = 4;
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break;
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}
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}
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/* Decode imm v64(Iv/Ov) */
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static void __get_immv(struct insn *insn)
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{
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switch (insn->opnd_bytes) {
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case 2:
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insn->immediate1.value = get_next(short, insn);
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insn->immediate1.nbytes = 2;
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break;
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case 4:
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insn->immediate1.value = get_next(int, insn);
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insn->immediate1.nbytes = 4;
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break;
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case 8:
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insn->immediate1.value = get_next(int, insn);
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insn->immediate1.nbytes = 4;
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insn->immediate2.value = get_next(int, insn);
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insn->immediate2.nbytes = 4;
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break;
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}
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insn->immediate1.got = insn->immediate2.got = 1;
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}
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/* Decode ptr16:16/32(Ap) */
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static void __get_immptr(struct insn *insn)
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{
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switch (insn->opnd_bytes) {
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case 2:
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insn->immediate1.value = get_next(short, insn);
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insn->immediate1.nbytes = 2;
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break;
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case 4:
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insn->immediate1.value = get_next(int, insn);
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insn->immediate1.nbytes = 4;
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break;
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case 8:
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/* ptr16:64 is not exist (no segment) */
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return;
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}
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insn->immediate2.value = get_next(unsigned short, insn);
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insn->immediate2.nbytes = 2;
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insn->immediate1.got = insn->immediate2.got = 1;
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}
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/**
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* insn_get_immediate() - Get the immediates of instruction
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* @insn: &struct insn containing instruction
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*
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* If necessary, first collects the instruction up to and including the
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* displacement bytes.
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* Basically, most of immediates are sign-expanded. Unsigned-value can be
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* get by bit masking with ((1 << (nbytes * 8)) - 1)
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*/
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void insn_get_immediate(struct insn *insn)
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{
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if (insn->immediate.got)
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return;
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if (!insn->displacement.got)
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insn_get_displacement(insn);
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if (inat_has_moffset(insn->attr)) {
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__get_moffset(insn);
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goto done;
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}
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if (!inat_has_immediate(insn->attr))
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/* no immediates */
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goto done;
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switch (inat_immediate_size(insn->attr)) {
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case INAT_IMM_BYTE:
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insn->immediate.value = get_next(char, insn);
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insn->immediate.nbytes = 1;
|
|
break;
|
|
case INAT_IMM_WORD:
|
|
insn->immediate.value = get_next(short, insn);
|
|
insn->immediate.nbytes = 2;
|
|
break;
|
|
case INAT_IMM_DWORD:
|
|
insn->immediate.value = get_next(int, insn);
|
|
insn->immediate.nbytes = 4;
|
|
break;
|
|
case INAT_IMM_QWORD:
|
|
insn->immediate1.value = get_next(int, insn);
|
|
insn->immediate1.nbytes = 4;
|
|
insn->immediate2.value = get_next(int, insn);
|
|
insn->immediate2.nbytes = 4;
|
|
break;
|
|
case INAT_IMM_PTR:
|
|
__get_immptr(insn);
|
|
break;
|
|
case INAT_IMM_VWORD32:
|
|
__get_immv32(insn);
|
|
break;
|
|
case INAT_IMM_VWORD:
|
|
__get_immv(insn);
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
if (inat_has_second_immediate(insn->attr)) {
|
|
insn->immediate2.value = get_next(char, insn);
|
|
insn->immediate2.nbytes = 1;
|
|
}
|
|
done:
|
|
insn->immediate.got = 1;
|
|
}
|
|
|
|
/**
|
|
* insn_get_length() - Get the length of instruction
|
|
* @insn: &struct insn containing instruction
|
|
*
|
|
* If necessary, first collects the instruction up to and including the
|
|
* immediates bytes.
|
|
*/
|
|
void insn_get_length(struct insn *insn)
|
|
{
|
|
if (insn->length)
|
|
return;
|
|
if (!insn->immediate.got)
|
|
insn_get_immediate(insn);
|
|
insn->length = (unsigned char)((unsigned long)insn->next_byte
|
|
- (unsigned long)insn->kaddr);
|
|
}
|