Andre Przywara e7fea0b9d0 net: axienet: Improve DMA error handling ... Since 0 is a valid DMA address, we cannot use the physical address to check whether a TX descriptor is valid and is holding a DMA mapping. Use the "cntrl" member of the descriptor to make this decision, as it contains at least the length of the buffer, so 0 points to an uninitialised buffer. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: David S. Miller <davem@davemloft.net>		2020-03-24 16:33:04 -07:00
..
Kconfig	net: xilinx: temac: Relax Kconfig dependencies	2020-03-24 16:33:04 -07:00
ll_temac_main.c	net: ll_temac: let core reject the unsupported coalescing parameters	2020-03-17 20:56:58 -07:00
ll_temac_mdio.c	net: ll_temac: Prepare indirect register access for multicast support	2019-05-23 09:33:57 -07:00
ll_temac.h	net: ll_temac: Add ethtool support for coalesce parameters	2020-02-29 21:30:43 -08:00
Makefile
xilinx_axienet_main.c	net: axienet: Improve DMA error handling	2020-03-24 16:33:04 -07:00
xilinx_axienet_mdio.c	net: axienet: Fix MDIO bus parent node detection	2019-06-06 16:24:30 -07:00
xilinx_axienet.h	net: axienet: Convert DMA error handler to a work queue	2020-03-24 16:33:04 -07:00
xilinx_emaclite.c	netdev: pass the stuck queue to the timeout handler	2019-12-12 21:38:57 -08:00