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e7f4da4c44
The reason why this was originally commented out is no longer clear. The UPHY driver for SATA works fine with or without this change. The reset value of the XDIGCLK_EN bit is 0, so unless programmed by the bootloader this shouldn't make a difference anyway. Define a macro for this bit and uncomment the code. This also fixes a coverity issue brought to my attention by Rohith because not only is the XDIGCLK_EN field modification commented out, but also the register write which causes none of the earlier modifications of the register value to be written to the register and the value being overwritten. Reported-by: Rohith Seelaboyina <rseelaboyina@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com> |
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| Kconfig | ||
| Makefile | ||
| phy-core.c | ||
| phy-lpc18xx-usb-otg.c | ||
| phy-pistachio-usb.c | ||
| phy-xgene.c | ||