mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-18 04:56:46 +07:00
98a1405e20
The Seaboard device tree supports all the features that the Seaboard board files support. Hence, there's no need to keep the board files around any more; all users should convert to device tree. MACH_KAEN and MACH_WARIO are also removed. While tegra-seaboard.dts doesn't support those explicitly, it would be trivial to create device trees for those boards if anyone cares. The Seaboard device tree is now compiled if Tegra2 support is enabled, rather than when Seaboard support is enabled. Signed-off-by: Stephen Warren <swarren@nvidia.com>
144 lines
3.6 KiB
Plaintext
144 lines
3.6 KiB
Plaintext
if ARCH_TEGRA
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comment "NVIDIA Tegra options"
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config ARCH_TEGRA_2x_SOC
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bool "Enable support for Tegra20 family"
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select CPU_V7
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select ARM_GIC
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select ARCH_REQUIRE_GPIOLIB
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select PINCTRL
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select PINCTRL_TEGRA20
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select USB_ARCH_HAS_EHCI if USB_SUPPORT
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select USB_ULPI if USB
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select USB_ULPI_VIEWPORT if USB_SUPPORT
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select ARM_ERRATA_720789
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select ARM_ERRATA_742230
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select ARM_ERRATA_751472
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select ARM_ERRATA_754327
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select ARM_ERRATA_764369
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select PL310_ERRATA_727915 if CACHE_L2X0
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select PL310_ERRATA_769419 if CACHE_L2X0
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select CPU_FREQ_TABLE if CPU_FREQ
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help
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Support for NVIDIA Tegra AP20 and T20 processors, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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config ARCH_TEGRA_3x_SOC
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bool "Enable support for Tegra30 family"
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select CPU_V7
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select ARM_GIC
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select ARCH_REQUIRE_GPIOLIB
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select PINCTRL
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select PINCTRL_TEGRA30
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select USB_ARCH_HAS_EHCI if USB_SUPPORT
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select USB_ULPI if USB
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select USB_ULPI_VIEWPORT if USB_SUPPORT
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select USE_OF
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select ARM_ERRATA_743622
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select ARM_ERRATA_751472
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select ARM_ERRATA_754322
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select ARM_ERRATA_764369
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select PL310_ERRATA_769419 if CACHE_L2X0
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select CPU_FREQ_TABLE if CPU_FREQ
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help
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Support for NVIDIA Tegra T30 processor family, based on the
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ARM CortexA9MP CPU and the ARM PL310 L2 cache controller
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config TEGRA_PCI
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bool "PCI Express support"
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depends on ARCH_TEGRA_2x_SOC
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select PCI
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config TEGRA_AHB
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bool "Enable AHB driver for NVIDIA Tegra SoCs"
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default y
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help
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Adds AHB configuration functionality for NVIDIA Tegra SoCs,
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which controls AHB bus master arbitration and some
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perfomance parameters(priority, prefech size).
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comment "Tegra board type"
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config MACH_HARMONY
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bool "Harmony board"
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depends on ARCH_TEGRA_2x_SOC
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help
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Support for nVidia Harmony development platform
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config MACH_PAZ00
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bool "Paz00 board"
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depends on ARCH_TEGRA_2x_SOC
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help
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Support for the Toshiba AC100/Dynabook AZ netbook
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config MACH_TRIMSLICE
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bool "TrimSlice board"
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depends on ARCH_TEGRA_2x_SOC
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select TEGRA_PCI
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help
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Support for CompuLab TrimSlice platform
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choice
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prompt "Default low-level debug console UART"
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default TEGRA_DEBUG_UART_NONE
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config TEGRA_DEBUG_UART_NONE
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bool "None"
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config TEGRA_DEBUG_UARTA
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bool "UART-A"
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config TEGRA_DEBUG_UARTB
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bool "UART-B"
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config TEGRA_DEBUG_UARTC
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bool "UART-C"
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config TEGRA_DEBUG_UARTD
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bool "UART-D"
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config TEGRA_DEBUG_UARTE
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bool "UART-E"
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endchoice
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choice
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prompt "Automatic low-level debug console UART"
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default TEGRA_DEBUG_UART_AUTO_NONE
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config TEGRA_DEBUG_UART_AUTO_NONE
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bool "None"
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config TEGRA_DEBUG_UART_AUTO_ODMDATA
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bool "Via ODMDATA"
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help
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Automatically determines which UART to use for low-level debug based
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on the ODMDATA value. This value is part of the BCT, and is written
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to the boot memory device using nvflash, or other flashing tool.
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When bits 19:18 are 3, then bits 17:15 indicate which UART to use;
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0/1/2/3/4 are UART A/B/C/D/E.
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config TEGRA_DEBUG_UART_AUTO_SCRATCH
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bool "Via UART scratch register"
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help
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Automatically determines which UART to use for low-level debug based
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on the UART scratch register value. Some bootloaders put ASCII 'D'
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in this register when they initialize their own console UART output.
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Using this option allows the kernel to automatically pick the same
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UART.
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endchoice
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config TEGRA_SYSTEM_DMA
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bool "Enable system DMA driver for NVIDIA Tegra SoCs"
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default y
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help
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Adds system DMA functionality for NVIDIA Tegra SoCs, used by
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several Tegra device drivers
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config TEGRA_EMC_SCALING_ENABLE
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bool "Enable scaling the memory frequency"
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endif
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