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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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e721295185
We can remove the extra code of modify_scu_cpu_psr() and use the cleaner generic ARM helper scu_power_mode(). As every CPU only deals with its own power register and scu_power_mode() operates with 8-bit accesses, we save the locking overhead too. Signed-off-by: Bastian Hecht <hechtb@gmail.com> Signed-off-by: Simon Horman <horms@verge.net.au>
128 lines
3.3 KiB
C
128 lines
3.3 KiB
C
/*
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* SMP support for R-Mobile / SH-Mobile - sh73a0 portion
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*
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* Copyright (C) 2010 Magnus Damm
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* Copyright (C) 2010 Takashi Yoshii
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/smp.h>
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#include <linux/spinlock.h>
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#include <linux/io.h>
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#include <linux/delay.h>
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#include <mach/common.h>
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#include <asm/smp_plat.h>
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#include <mach/sh73a0.h>
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#include <asm/smp_scu.h>
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#include <asm/smp_twd.h>
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#include <asm/hardware/gic.h>
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#define WUPCR IOMEM(0xe6151010)
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#define SRESCR IOMEM(0xe6151018)
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#define PSTR IOMEM(0xe6151040)
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#define SBAR IOMEM(0xe6180020)
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#define APARMBAREA IOMEM(0xe6f10020)
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static void __iomem *scu_base_addr(void)
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{
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return (void __iomem *)0xf0000000;
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}
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#ifdef CONFIG_HAVE_ARM_TWD
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static DEFINE_TWD_LOCAL_TIMER(twd_local_timer, 0xf0000600, 29);
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void __init sh73a0_register_twd(void)
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{
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twd_local_timer_register(&twd_local_timer);
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}
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#endif
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static unsigned int __init sh73a0_get_core_count(void)
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{
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void __iomem *scu_base = scu_base_addr();
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return scu_get_core_count(scu_base);
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}
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static void __cpuinit sh73a0_secondary_init(unsigned int cpu)
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{
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gic_secondary_init(0);
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}
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static int __cpuinit sh73a0_boot_secondary(unsigned int cpu, struct task_struct *idle)
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{
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cpu = cpu_logical_map(cpu);
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/* enable cache coherency */
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scu_power_mode(scu_base_addr(), 0);
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if (((__raw_readl(PSTR) >> (4 * cpu)) & 3) == 3)
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__raw_writel(1 << cpu, WUPCR); /* wake up */
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else
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__raw_writel(1 << cpu, SRESCR); /* reset */
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return 0;
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}
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static void __init sh73a0_smp_prepare_cpus(unsigned int max_cpus)
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{
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scu_enable(scu_base_addr());
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/* Map the reset vector (in headsmp.S) */
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__raw_writel(0, APARMBAREA); /* 4k */
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__raw_writel(__pa(shmobile_secondary_vector), SBAR);
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/* enable cache coherency on CPU0 */
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scu_power_mode(scu_base_addr(), 0);
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}
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static void __init sh73a0_smp_init_cpus(void)
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{
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unsigned int ncores = sh73a0_get_core_count();
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shmobile_smp_init_cpus(ncores);
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}
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static int __maybe_unused sh73a0_cpu_kill(unsigned int cpu)
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{
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int k;
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/* this function is running on another CPU than the offline target,
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* here we need wait for shutdown code in platform_cpu_die() to
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* finish before asking SoC-specific code to power off the CPU core.
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*/
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for (k = 0; k < 1000; k++) {
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if (shmobile_cpu_is_dead(cpu))
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return 1;
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mdelay(1);
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}
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return 0;
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}
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struct smp_operations sh73a0_smp_ops __initdata = {
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.smp_init_cpus = sh73a0_smp_init_cpus,
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.smp_prepare_cpus = sh73a0_smp_prepare_cpus,
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.smp_secondary_init = sh73a0_secondary_init,
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.smp_boot_secondary = sh73a0_boot_secondary,
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#ifdef CONFIG_HOTPLUG_CPU
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.cpu_kill = sh73a0_cpu_kill,
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.cpu_die = shmobile_cpu_die,
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.cpu_disable = shmobile_cpu_disable,
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#endif
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};
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