mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-05 10:46:40 +07:00
d4fc72ed15
Create distinct compatible strings for mdp4 and mdp5. Keep "qcom,mdss_mdp" as is to support downstream kernels. Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
1140 lines
26 KiB
C
1140 lines
26 KiB
C
/*
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "msm_drv.h"
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#include "msm_gpu.h"
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#include "msm_kms.h"
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static void msm_fb_output_poll_changed(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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if (priv->fbdev)
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drm_fb_helper_hotplug_event(priv->fbdev);
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}
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static const struct drm_mode_config_funcs mode_config_funcs = {
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.fb_create = msm_framebuffer_create,
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.output_poll_changed = msm_fb_output_poll_changed,
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.atomic_check = msm_atomic_check,
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.atomic_commit = msm_atomic_commit,
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};
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int msm_register_mmu(struct drm_device *dev, struct msm_mmu *mmu)
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{
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struct msm_drm_private *priv = dev->dev_private;
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int idx = priv->num_mmus++;
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if (WARN_ON(idx >= ARRAY_SIZE(priv->mmus)))
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return -EINVAL;
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priv->mmus[idx] = mmu;
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return idx;
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}
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#ifdef CONFIG_DRM_MSM_REGISTER_LOGGING
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static bool reglog = false;
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MODULE_PARM_DESC(reglog, "Enable register read/write logging");
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module_param(reglog, bool, 0600);
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#else
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#define reglog 0
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#endif
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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static bool fbdev = true;
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MODULE_PARM_DESC(fbdev, "Enable fbdev compat layer");
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module_param(fbdev, bool, 0600);
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#endif
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static char *vram = "16m";
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MODULE_PARM_DESC(vram, "Configure VRAM size (for devices without IOMMU/GPUMMU");
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module_param(vram, charp, 0);
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/*
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* Util/helpers:
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*/
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void __iomem *msm_ioremap(struct platform_device *pdev, const char *name,
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const char *dbgname)
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{
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struct resource *res;
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unsigned long size;
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void __iomem *ptr;
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if (name)
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res = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
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else
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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if (!res) {
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dev_err(&pdev->dev, "failed to get memory resource: %s\n", name);
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return ERR_PTR(-EINVAL);
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}
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size = resource_size(res);
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ptr = devm_ioremap_nocache(&pdev->dev, res->start, size);
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if (!ptr) {
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dev_err(&pdev->dev, "failed to ioremap: %s\n", name);
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return ERR_PTR(-ENOMEM);
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}
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if (reglog)
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printk(KERN_DEBUG "IO:region %s %p %08lx\n", dbgname, ptr, size);
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return ptr;
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}
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void msm_writel(u32 data, void __iomem *addr)
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{
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if (reglog)
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printk(KERN_DEBUG "IO:W %p %08x\n", addr, data);
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writel(data, addr);
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}
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u32 msm_readl(const void __iomem *addr)
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{
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u32 val = readl(addr);
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if (reglog)
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printk(KERN_ERR "IO:R %p %08x\n", addr, val);
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return val;
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}
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struct vblank_event {
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struct list_head node;
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int crtc_id;
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bool enable;
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};
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static void vblank_ctrl_worker(struct work_struct *work)
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{
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struct msm_vblank_ctrl *vbl_ctrl = container_of(work,
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struct msm_vblank_ctrl, work);
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struct msm_drm_private *priv = container_of(vbl_ctrl,
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struct msm_drm_private, vblank_ctrl);
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struct msm_kms *kms = priv->kms;
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struct vblank_event *vbl_ev, *tmp;
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unsigned long flags;
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spin_lock_irqsave(&vbl_ctrl->lock, flags);
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list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
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list_del(&vbl_ev->node);
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spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
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if (vbl_ev->enable)
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kms->funcs->enable_vblank(kms,
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priv->crtcs[vbl_ev->crtc_id]);
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else
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kms->funcs->disable_vblank(kms,
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priv->crtcs[vbl_ev->crtc_id]);
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kfree(vbl_ev);
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spin_lock_irqsave(&vbl_ctrl->lock, flags);
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}
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spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
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}
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static int vblank_ctrl_queue_work(struct msm_drm_private *priv,
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int crtc_id, bool enable)
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{
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struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
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struct vblank_event *vbl_ev;
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unsigned long flags;
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vbl_ev = kzalloc(sizeof(*vbl_ev), GFP_ATOMIC);
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if (!vbl_ev)
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return -ENOMEM;
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vbl_ev->crtc_id = crtc_id;
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vbl_ev->enable = enable;
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spin_lock_irqsave(&vbl_ctrl->lock, flags);
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list_add_tail(&vbl_ev->node, &vbl_ctrl->event_list);
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spin_unlock_irqrestore(&vbl_ctrl->lock, flags);
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queue_work(priv->wq, &vbl_ctrl->work);
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return 0;
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}
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/*
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* DRM operations:
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*/
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static int msm_unload(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_kms *kms = priv->kms;
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struct msm_gpu *gpu = priv->gpu;
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struct msm_vblank_ctrl *vbl_ctrl = &priv->vblank_ctrl;
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struct vblank_event *vbl_ev, *tmp;
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/* We must cancel and cleanup any pending vblank enable/disable
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* work before drm_irq_uninstall() to avoid work re-enabling an
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* irq after uninstall has disabled it.
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*/
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cancel_work_sync(&vbl_ctrl->work);
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list_for_each_entry_safe(vbl_ev, tmp, &vbl_ctrl->event_list, node) {
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list_del(&vbl_ev->node);
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kfree(vbl_ev);
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}
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drm_kms_helper_poll_fini(dev);
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drm_mode_config_cleanup(dev);
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drm_vblank_cleanup(dev);
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pm_runtime_get_sync(dev->dev);
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drm_irq_uninstall(dev);
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pm_runtime_put_sync(dev->dev);
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flush_workqueue(priv->wq);
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destroy_workqueue(priv->wq);
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if (kms) {
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pm_runtime_disable(dev->dev);
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kms->funcs->destroy(kms);
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}
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if (gpu) {
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mutex_lock(&dev->struct_mutex);
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gpu->funcs->pm_suspend(gpu);
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mutex_unlock(&dev->struct_mutex);
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gpu->funcs->destroy(gpu);
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}
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if (priv->vram.paddr) {
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DEFINE_DMA_ATTRS(attrs);
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dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
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drm_mm_takedown(&priv->vram.mm);
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dma_free_attrs(dev->dev, priv->vram.size, NULL,
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priv->vram.paddr, &attrs);
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}
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component_unbind_all(dev->dev, dev);
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dev->dev_private = NULL;
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kfree(priv);
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return 0;
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}
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static int get_mdp_ver(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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return (int) (unsigned long) of_device_get_match_data(dev);
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}
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#include <linux/of_address.h>
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static int msm_init_vram(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct device_node *node;
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unsigned long size = 0;
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int ret = 0;
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/* In the device-tree world, we could have a 'memory-region'
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* phandle, which gives us a link to our "vram". Allocating
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* is all nicely abstracted behind the dma api, but we need
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* to know the entire size to allocate it all in one go. There
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* are two cases:
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* 1) device with no IOMMU, in which case we need exclusive
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* access to a VRAM carveout big enough for all gpu
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* buffers
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* 2) device with IOMMU, but where the bootloader puts up
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* a splash screen. In this case, the VRAM carveout
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* need only be large enough for fbdev fb. But we need
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* exclusive access to the buffer to avoid the kernel
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* using those pages for other purposes (which appears
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* as corruption on screen before we have a chance to
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* load and do initial modeset)
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*/
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node = of_parse_phandle(dev->dev->of_node, "memory-region", 0);
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if (node) {
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struct resource r;
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ret = of_address_to_resource(node, 0, &r);
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if (ret)
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return ret;
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size = r.end - r.start;
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DRM_INFO("using VRAM carveout: %lx@%pa\n", size, &r.start);
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/* if we have no IOMMU, then we need to use carveout allocator.
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* Grab the entire CMA chunk carved out in early startup in
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* mach-msm:
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*/
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} else if (!iommu_present(&platform_bus_type)) {
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DRM_INFO("using %s VRAM carveout\n", vram);
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size = memparse(vram, NULL);
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}
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if (size) {
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DEFINE_DMA_ATTRS(attrs);
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void *p;
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priv->vram.size = size;
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drm_mm_init(&priv->vram.mm, 0, (size >> PAGE_SHIFT) - 1);
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dma_set_attr(DMA_ATTR_NO_KERNEL_MAPPING, &attrs);
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dma_set_attr(DMA_ATTR_WRITE_COMBINE, &attrs);
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/* note that for no-kernel-mapping, the vaddr returned
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* is bogus, but non-null if allocation succeeded:
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*/
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p = dma_alloc_attrs(dev->dev, size,
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&priv->vram.paddr, GFP_KERNEL, &attrs);
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if (!p) {
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dev_err(dev->dev, "failed to allocate VRAM\n");
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priv->vram.paddr = 0;
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return -ENOMEM;
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}
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dev_info(dev->dev, "VRAM: %08x->%08x\n",
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(uint32_t)priv->vram.paddr,
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(uint32_t)(priv->vram.paddr + size));
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}
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return ret;
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}
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static int msm_load(struct drm_device *dev, unsigned long flags)
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{
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struct platform_device *pdev = dev->platformdev;
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struct msm_drm_private *priv;
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struct msm_kms *kms;
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int ret;
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priv = kzalloc(sizeof(*priv), GFP_KERNEL);
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if (!priv) {
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dev_err(dev->dev, "failed to allocate private data\n");
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return -ENOMEM;
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}
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dev->dev_private = priv;
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priv->wq = alloc_ordered_workqueue("msm", 0);
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init_waitqueue_head(&priv->fence_event);
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init_waitqueue_head(&priv->pending_crtcs_event);
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INIT_LIST_HEAD(&priv->inactive_list);
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INIT_LIST_HEAD(&priv->fence_cbs);
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INIT_LIST_HEAD(&priv->vblank_ctrl.event_list);
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INIT_WORK(&priv->vblank_ctrl.work, vblank_ctrl_worker);
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spin_lock_init(&priv->vblank_ctrl.lock);
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drm_mode_config_init(dev);
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platform_set_drvdata(pdev, dev);
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/* Bind all our sub-components: */
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ret = component_bind_all(dev->dev, dev);
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if (ret)
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return ret;
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ret = msm_init_vram(dev);
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if (ret)
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goto fail;
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switch (get_mdp_ver(pdev)) {
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case 4:
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kms = mdp4_kms_init(dev);
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break;
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case 5:
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kms = mdp5_kms_init(dev);
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break;
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default:
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kms = ERR_PTR(-ENODEV);
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break;
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}
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if (IS_ERR(kms)) {
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/*
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* NOTE: once we have GPU support, having no kms should not
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* be considered fatal.. ideally we would still support gpu
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* and (for example) use dmabuf/prime to share buffers with
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* imx drm driver on iMX5
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*/
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dev_err(dev->dev, "failed to load kms\n");
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ret = PTR_ERR(kms);
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goto fail;
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}
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priv->kms = kms;
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if (kms) {
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pm_runtime_enable(dev->dev);
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ret = kms->funcs->hw_init(kms);
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if (ret) {
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dev_err(dev->dev, "kms hw init failed: %d\n", ret);
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goto fail;
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}
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}
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dev->mode_config.funcs = &mode_config_funcs;
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ret = drm_vblank_init(dev, priv->num_crtcs);
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if (ret < 0) {
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dev_err(dev->dev, "failed to initialize vblank\n");
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goto fail;
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}
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pm_runtime_get_sync(dev->dev);
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ret = drm_irq_install(dev, platform_get_irq(dev->platformdev, 0));
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pm_runtime_put_sync(dev->dev);
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if (ret < 0) {
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dev_err(dev->dev, "failed to install IRQ handler\n");
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goto fail;
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}
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drm_mode_config_reset(dev);
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#ifdef CONFIG_DRM_FBDEV_EMULATION
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if (fbdev)
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priv->fbdev = msm_fbdev_init(dev);
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#endif
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ret = msm_debugfs_late_init(dev);
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if (ret)
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goto fail;
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drm_kms_helper_poll_init(dev);
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return 0;
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fail:
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msm_unload(dev);
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return ret;
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}
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static void load_gpu(struct drm_device *dev)
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{
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static DEFINE_MUTEX(init_lock);
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struct msm_drm_private *priv = dev->dev_private;
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mutex_lock(&init_lock);
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if (!priv->gpu)
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priv->gpu = adreno_load_gpu(dev);
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mutex_unlock(&init_lock);
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}
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static int msm_open(struct drm_device *dev, struct drm_file *file)
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{
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struct msm_file_private *ctx;
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/* For now, load gpu on open.. to avoid the requirement of having
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* firmware in the initrd.
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*/
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load_gpu(dev);
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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file->driver_priv = ctx;
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return 0;
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}
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static void msm_preclose(struct drm_device *dev, struct drm_file *file)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_file_private *ctx = file->driver_priv;
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struct msm_kms *kms = priv->kms;
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if (kms)
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kms->funcs->preclose(kms, file);
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mutex_lock(&dev->struct_mutex);
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if (ctx == priv->lastctx)
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priv->lastctx = NULL;
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mutex_unlock(&dev->struct_mutex);
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kfree(ctx);
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}
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static void msm_lastclose(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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if (priv->fbdev)
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drm_fb_helper_restore_fbdev_mode_unlocked(priv->fbdev);
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}
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|
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static irqreturn_t msm_irq(int irq, void *arg)
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{
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struct drm_device *dev = arg;
|
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_kms *kms = priv->kms;
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BUG_ON(!kms);
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return kms->funcs->irq(kms);
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}
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|
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static void msm_irq_preinstall(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_kms *kms = priv->kms;
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BUG_ON(!kms);
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kms->funcs->irq_preinstall(kms);
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}
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|
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static int msm_irq_postinstall(struct drm_device *dev)
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{
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struct msm_drm_private *priv = dev->dev_private;
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struct msm_kms *kms = priv->kms;
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BUG_ON(!kms);
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return kms->funcs->irq_postinstall(kms);
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}
|
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|
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static void msm_irq_uninstall(struct drm_device *dev)
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{
|
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struct msm_drm_private *priv = dev->dev_private;
|
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struct msm_kms *kms = priv->kms;
|
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BUG_ON(!kms);
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kms->funcs->irq_uninstall(kms);
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}
|
|
|
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static int msm_enable_vblank(struct drm_device *dev, unsigned int pipe)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct msm_kms *kms = priv->kms;
|
|
if (!kms)
|
|
return -ENXIO;
|
|
DBG("dev=%p, crtc=%u", dev, pipe);
|
|
return vblank_ctrl_queue_work(priv, pipe, true);
|
|
}
|
|
|
|
static void msm_disable_vblank(struct drm_device *dev, unsigned int pipe)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct msm_kms *kms = priv->kms;
|
|
if (!kms)
|
|
return;
|
|
DBG("dev=%p, crtc=%u", dev, pipe);
|
|
vblank_ctrl_queue_work(priv, pipe, false);
|
|
}
|
|
|
|
/*
|
|
* DRM debugfs:
|
|
*/
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
static int msm_gpu_show(struct drm_device *dev, struct seq_file *m)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct msm_gpu *gpu = priv->gpu;
|
|
|
|
if (gpu) {
|
|
seq_printf(m, "%s Status:\n", gpu->name);
|
|
gpu->funcs->show(gpu, m);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int msm_gem_show(struct drm_device *dev, struct seq_file *m)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct msm_gpu *gpu = priv->gpu;
|
|
|
|
if (gpu) {
|
|
seq_printf(m, "Active Objects (%s):\n", gpu->name);
|
|
msm_gem_describe_objects(&gpu->active_list, m);
|
|
}
|
|
|
|
seq_printf(m, "Inactive Objects:\n");
|
|
msm_gem_describe_objects(&priv->inactive_list, m);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int msm_mm_show(struct drm_device *dev, struct seq_file *m)
|
|
{
|
|
return drm_mm_dump_table(m, &dev->vma_offset_manager->vm_addr_space_mm);
|
|
}
|
|
|
|
static int msm_fb_show(struct drm_device *dev, struct seq_file *m)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct drm_framebuffer *fb, *fbdev_fb = NULL;
|
|
|
|
if (priv->fbdev) {
|
|
seq_printf(m, "fbcon ");
|
|
fbdev_fb = priv->fbdev->fb;
|
|
msm_framebuffer_describe(fbdev_fb, m);
|
|
}
|
|
|
|
mutex_lock(&dev->mode_config.fb_lock);
|
|
list_for_each_entry(fb, &dev->mode_config.fb_list, head) {
|
|
if (fb == fbdev_fb)
|
|
continue;
|
|
|
|
seq_printf(m, "user ");
|
|
msm_framebuffer_describe(fb, m);
|
|
}
|
|
mutex_unlock(&dev->mode_config.fb_lock);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int show_locked(struct seq_file *m, void *arg)
|
|
{
|
|
struct drm_info_node *node = (struct drm_info_node *) m->private;
|
|
struct drm_device *dev = node->minor->dev;
|
|
int (*show)(struct drm_device *dev, struct seq_file *m) =
|
|
node->info_ent->data;
|
|
int ret;
|
|
|
|
ret = mutex_lock_interruptible(&dev->struct_mutex);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = show(dev, m);
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static struct drm_info_list msm_debugfs_list[] = {
|
|
{"gpu", show_locked, 0, msm_gpu_show},
|
|
{"gem", show_locked, 0, msm_gem_show},
|
|
{ "mm", show_locked, 0, msm_mm_show },
|
|
{ "fb", show_locked, 0, msm_fb_show },
|
|
};
|
|
|
|
static int late_init_minor(struct drm_minor *minor)
|
|
{
|
|
int ret;
|
|
|
|
if (!minor)
|
|
return 0;
|
|
|
|
ret = msm_rd_debugfs_init(minor);
|
|
if (ret) {
|
|
dev_err(minor->dev->dev, "could not install rd debugfs\n");
|
|
return ret;
|
|
}
|
|
|
|
ret = msm_perf_debugfs_init(minor);
|
|
if (ret) {
|
|
dev_err(minor->dev->dev, "could not install perf debugfs\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
int msm_debugfs_late_init(struct drm_device *dev)
|
|
{
|
|
int ret;
|
|
ret = late_init_minor(dev->primary);
|
|
if (ret)
|
|
return ret;
|
|
ret = late_init_minor(dev->render);
|
|
if (ret)
|
|
return ret;
|
|
ret = late_init_minor(dev->control);
|
|
return ret;
|
|
}
|
|
|
|
static int msm_debugfs_init(struct drm_minor *minor)
|
|
{
|
|
struct drm_device *dev = minor->dev;
|
|
int ret;
|
|
|
|
ret = drm_debugfs_create_files(msm_debugfs_list,
|
|
ARRAY_SIZE(msm_debugfs_list),
|
|
minor->debugfs_root, minor);
|
|
|
|
if (ret) {
|
|
dev_err(dev->dev, "could not install msm_debugfs_list\n");
|
|
return ret;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void msm_debugfs_cleanup(struct drm_minor *minor)
|
|
{
|
|
drm_debugfs_remove_files(msm_debugfs_list,
|
|
ARRAY_SIZE(msm_debugfs_list), minor);
|
|
if (!minor->dev->dev_private)
|
|
return;
|
|
msm_rd_debugfs_cleanup(minor);
|
|
msm_perf_debugfs_cleanup(minor);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Fences:
|
|
*/
|
|
|
|
int msm_wait_fence(struct drm_device *dev, uint32_t fence,
|
|
ktime_t *timeout , bool interruptible)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
int ret;
|
|
|
|
if (!priv->gpu)
|
|
return 0;
|
|
|
|
if (fence > priv->gpu->submitted_fence) {
|
|
DRM_ERROR("waiting on invalid fence: %u (of %u)\n",
|
|
fence, priv->gpu->submitted_fence);
|
|
return -EINVAL;
|
|
}
|
|
|
|
if (!timeout) {
|
|
/* no-wait: */
|
|
ret = fence_completed(dev, fence) ? 0 : -EBUSY;
|
|
} else {
|
|
ktime_t now = ktime_get();
|
|
unsigned long remaining_jiffies;
|
|
|
|
if (ktime_compare(*timeout, now) < 0) {
|
|
remaining_jiffies = 0;
|
|
} else {
|
|
ktime_t rem = ktime_sub(*timeout, now);
|
|
struct timespec ts = ktime_to_timespec(rem);
|
|
remaining_jiffies = timespec_to_jiffies(&ts);
|
|
}
|
|
|
|
if (interruptible)
|
|
ret = wait_event_interruptible_timeout(priv->fence_event,
|
|
fence_completed(dev, fence),
|
|
remaining_jiffies);
|
|
else
|
|
ret = wait_event_timeout(priv->fence_event,
|
|
fence_completed(dev, fence),
|
|
remaining_jiffies);
|
|
|
|
if (ret == 0) {
|
|
DBG("timeout waiting for fence: %u (completed: %u)",
|
|
fence, priv->completed_fence);
|
|
ret = -ETIMEDOUT;
|
|
} else if (ret != -ERESTARTSYS) {
|
|
ret = 0;
|
|
}
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
int msm_queue_fence_cb(struct drm_device *dev,
|
|
struct msm_fence_cb *cb, uint32_t fence)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
int ret = 0;
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
if (!list_empty(&cb->work.entry)) {
|
|
ret = -EINVAL;
|
|
} else if (fence > priv->completed_fence) {
|
|
cb->fence = fence;
|
|
list_add_tail(&cb->work.entry, &priv->fence_cbs);
|
|
} else {
|
|
queue_work(priv->wq, &cb->work);
|
|
}
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/* called from workqueue */
|
|
void msm_update_fence(struct drm_device *dev, uint32_t fence)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
|
|
mutex_lock(&dev->struct_mutex);
|
|
priv->completed_fence = max(fence, priv->completed_fence);
|
|
|
|
while (!list_empty(&priv->fence_cbs)) {
|
|
struct msm_fence_cb *cb;
|
|
|
|
cb = list_first_entry(&priv->fence_cbs,
|
|
struct msm_fence_cb, work.entry);
|
|
|
|
if (cb->fence > priv->completed_fence)
|
|
break;
|
|
|
|
list_del_init(&cb->work.entry);
|
|
queue_work(priv->wq, &cb->work);
|
|
}
|
|
|
|
mutex_unlock(&dev->struct_mutex);
|
|
|
|
wake_up_all(&priv->fence_event);
|
|
}
|
|
|
|
void __msm_fence_worker(struct work_struct *work)
|
|
{
|
|
struct msm_fence_cb *cb = container_of(work, struct msm_fence_cb, work);
|
|
cb->func(cb);
|
|
}
|
|
|
|
/*
|
|
* DRM ioctls:
|
|
*/
|
|
|
|
static int msm_ioctl_get_param(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct msm_drm_private *priv = dev->dev_private;
|
|
struct drm_msm_param *args = data;
|
|
struct msm_gpu *gpu;
|
|
|
|
/* for now, we just have 3d pipe.. eventually this would need to
|
|
* be more clever to dispatch to appropriate gpu module:
|
|
*/
|
|
if (args->pipe != MSM_PIPE_3D0)
|
|
return -EINVAL;
|
|
|
|
gpu = priv->gpu;
|
|
|
|
if (!gpu)
|
|
return -ENXIO;
|
|
|
|
return gpu->funcs->get_param(gpu, args->param, &args->value);
|
|
}
|
|
|
|
static int msm_ioctl_gem_new(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_msm_gem_new *args = data;
|
|
|
|
if (args->flags & ~MSM_BO_FLAGS) {
|
|
DRM_ERROR("invalid flags: %08x\n", args->flags);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return msm_gem_new_handle(dev, file, args->size,
|
|
args->flags, &args->handle);
|
|
}
|
|
|
|
static inline ktime_t to_ktime(struct drm_msm_timespec timeout)
|
|
{
|
|
return ktime_set(timeout.tv_sec, timeout.tv_nsec);
|
|
}
|
|
|
|
static int msm_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_msm_gem_cpu_prep *args = data;
|
|
struct drm_gem_object *obj;
|
|
ktime_t timeout = to_ktime(args->timeout);
|
|
int ret;
|
|
|
|
if (args->op & ~MSM_PREP_FLAGS) {
|
|
DRM_ERROR("invalid op: %08x\n", args->op);
|
|
return -EINVAL;
|
|
}
|
|
|
|
obj = drm_gem_object_lookup(dev, file, args->handle);
|
|
if (!obj)
|
|
return -ENOENT;
|
|
|
|
ret = msm_gem_cpu_prep(obj, args->op, &timeout);
|
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int msm_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_msm_gem_cpu_fini *args = data;
|
|
struct drm_gem_object *obj;
|
|
int ret;
|
|
|
|
obj = drm_gem_object_lookup(dev, file, args->handle);
|
|
if (!obj)
|
|
return -ENOENT;
|
|
|
|
ret = msm_gem_cpu_fini(obj);
|
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int msm_ioctl_gem_info(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_msm_gem_info *args = data;
|
|
struct drm_gem_object *obj;
|
|
int ret = 0;
|
|
|
|
if (args->pad)
|
|
return -EINVAL;
|
|
|
|
obj = drm_gem_object_lookup(dev, file, args->handle);
|
|
if (!obj)
|
|
return -ENOENT;
|
|
|
|
args->offset = msm_gem_mmap_offset(obj);
|
|
|
|
drm_gem_object_unreference_unlocked(obj);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int msm_ioctl_wait_fence(struct drm_device *dev, void *data,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_msm_wait_fence *args = data;
|
|
ktime_t timeout = to_ktime(args->timeout);
|
|
|
|
if (args->pad) {
|
|
DRM_ERROR("invalid pad: %08x\n", args->pad);
|
|
return -EINVAL;
|
|
}
|
|
|
|
return msm_wait_fence(dev, args->fence, &timeout, true);
|
|
}
|
|
|
|
static const struct drm_ioctl_desc msm_ioctls[] = {
|
|
DRM_IOCTL_DEF_DRV(MSM_GET_PARAM, msm_ioctl_get_param, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_NEW, msm_ioctl_gem_new, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_INFO, msm_ioctl_gem_info, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_PREP, msm_ioctl_gem_cpu_prep, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_CPU_FINI, msm_ioctl_gem_cpu_fini, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(MSM_GEM_SUBMIT, msm_ioctl_gem_submit, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
DRM_IOCTL_DEF_DRV(MSM_WAIT_FENCE, msm_ioctl_wait_fence, DRM_AUTH|DRM_RENDER_ALLOW),
|
|
};
|
|
|
|
static const struct vm_operations_struct vm_ops = {
|
|
.fault = msm_gem_fault,
|
|
.open = drm_gem_vm_open,
|
|
.close = drm_gem_vm_close,
|
|
};
|
|
|
|
static const struct file_operations fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.unlocked_ioctl = drm_ioctl,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl = drm_compat_ioctl,
|
|
#endif
|
|
.poll = drm_poll,
|
|
.read = drm_read,
|
|
.llseek = no_llseek,
|
|
.mmap = msm_gem_mmap,
|
|
};
|
|
|
|
static struct drm_driver msm_driver = {
|
|
.driver_features = DRIVER_HAVE_IRQ |
|
|
DRIVER_GEM |
|
|
DRIVER_PRIME |
|
|
DRIVER_RENDER |
|
|
DRIVER_ATOMIC |
|
|
DRIVER_MODESET,
|
|
.load = msm_load,
|
|
.unload = msm_unload,
|
|
.open = msm_open,
|
|
.preclose = msm_preclose,
|
|
.lastclose = msm_lastclose,
|
|
.set_busid = drm_platform_set_busid,
|
|
.irq_handler = msm_irq,
|
|
.irq_preinstall = msm_irq_preinstall,
|
|
.irq_postinstall = msm_irq_postinstall,
|
|
.irq_uninstall = msm_irq_uninstall,
|
|
.get_vblank_counter = drm_vblank_no_hw_counter,
|
|
.enable_vblank = msm_enable_vblank,
|
|
.disable_vblank = msm_disable_vblank,
|
|
.gem_free_object = msm_gem_free_object,
|
|
.gem_vm_ops = &vm_ops,
|
|
.dumb_create = msm_gem_dumb_create,
|
|
.dumb_map_offset = msm_gem_dumb_map_offset,
|
|
.dumb_destroy = drm_gem_dumb_destroy,
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
.gem_prime_export = drm_gem_prime_export,
|
|
.gem_prime_import = drm_gem_prime_import,
|
|
.gem_prime_pin = msm_gem_prime_pin,
|
|
.gem_prime_unpin = msm_gem_prime_unpin,
|
|
.gem_prime_get_sg_table = msm_gem_prime_get_sg_table,
|
|
.gem_prime_import_sg_table = msm_gem_prime_import_sg_table,
|
|
.gem_prime_vmap = msm_gem_prime_vmap,
|
|
.gem_prime_vunmap = msm_gem_prime_vunmap,
|
|
.gem_prime_mmap = msm_gem_prime_mmap,
|
|
#ifdef CONFIG_DEBUG_FS
|
|
.debugfs_init = msm_debugfs_init,
|
|
.debugfs_cleanup = msm_debugfs_cleanup,
|
|
#endif
|
|
.ioctls = msm_ioctls,
|
|
.num_ioctls = DRM_MSM_NUM_IOCTLS,
|
|
.fops = &fops,
|
|
.name = "msm",
|
|
.desc = "MSM Snapdragon DRM",
|
|
.date = "20130625",
|
|
.major = 1,
|
|
.minor = 0,
|
|
};
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int msm_pm_suspend(struct device *dev)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
|
|
drm_kms_helper_poll_disable(ddev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int msm_pm_resume(struct device *dev)
|
|
{
|
|
struct drm_device *ddev = dev_get_drvdata(dev);
|
|
|
|
drm_kms_helper_poll_enable(ddev);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops msm_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(msm_pm_suspend, msm_pm_resume)
|
|
};
|
|
|
|
/*
|
|
* Componentized driver support:
|
|
*/
|
|
|
|
/*
|
|
* NOTE: duplication of the same code as exynos or imx (or probably any other).
|
|
* so probably some room for some helpers
|
|
*/
|
|
static int compare_of(struct device *dev, void *data)
|
|
{
|
|
return dev->of_node == data;
|
|
}
|
|
|
|
static int add_components(struct device *dev, struct component_match **matchptr,
|
|
const char *name)
|
|
{
|
|
struct device_node *np = dev->of_node;
|
|
unsigned i;
|
|
|
|
for (i = 0; ; i++) {
|
|
struct device_node *node;
|
|
|
|
node = of_parse_phandle(np, name, i);
|
|
if (!node)
|
|
break;
|
|
|
|
component_match_add(dev, matchptr, compare_of, node);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int msm_drm_bind(struct device *dev)
|
|
{
|
|
return drm_platform_init(&msm_driver, to_platform_device(dev));
|
|
}
|
|
|
|
static void msm_drm_unbind(struct device *dev)
|
|
{
|
|
drm_put_dev(platform_get_drvdata(to_platform_device(dev)));
|
|
}
|
|
|
|
static const struct component_master_ops msm_drm_ops = {
|
|
.bind = msm_drm_bind,
|
|
.unbind = msm_drm_unbind,
|
|
};
|
|
|
|
/*
|
|
* Platform driver:
|
|
*/
|
|
|
|
static int msm_pdev_probe(struct platform_device *pdev)
|
|
{
|
|
struct component_match *match = NULL;
|
|
|
|
add_components(&pdev->dev, &match, "connectors");
|
|
add_components(&pdev->dev, &match, "gpus");
|
|
|
|
pdev->dev.coherent_dma_mask = DMA_BIT_MASK(32);
|
|
return component_master_add_with_match(&pdev->dev, &msm_drm_ops, match);
|
|
}
|
|
|
|
static int msm_pdev_remove(struct platform_device *pdev)
|
|
{
|
|
component_master_del(&pdev->dev, &msm_drm_ops);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id msm_id[] = {
|
|
{ "mdp", 0 },
|
|
{ }
|
|
};
|
|
|
|
static const struct of_device_id dt_match[] = {
|
|
{ .compatible = "qcom,mdp4", .data = (void *) 4 }, /* mdp4 */
|
|
{ .compatible = "qcom,mdp5", .data = (void *) 5 }, /* mdp5 */
|
|
/* to support downstream DT files */
|
|
{ .compatible = "qcom,mdss_mdp", .data = (void *) 5 }, /* mdp5 */
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dt_match);
|
|
|
|
static struct platform_driver msm_platform_driver = {
|
|
.probe = msm_pdev_probe,
|
|
.remove = msm_pdev_remove,
|
|
.driver = {
|
|
.name = "msm",
|
|
.of_match_table = dt_match,
|
|
.pm = &msm_pm_ops,
|
|
},
|
|
.id_table = msm_id,
|
|
};
|
|
|
|
static int __init msm_drm_register(void)
|
|
{
|
|
DBG("init");
|
|
msm_dsi_register();
|
|
msm_edp_register();
|
|
hdmi_register();
|
|
adreno_register();
|
|
return platform_driver_register(&msm_platform_driver);
|
|
}
|
|
|
|
static void __exit msm_drm_unregister(void)
|
|
{
|
|
DBG("fini");
|
|
platform_driver_unregister(&msm_platform_driver);
|
|
hdmi_unregister();
|
|
adreno_unregister();
|
|
msm_edp_unregister();
|
|
msm_dsi_unregister();
|
|
}
|
|
|
|
module_init(msm_drm_register);
|
|
module_exit(msm_drm_unregister);
|
|
|
|
MODULE_AUTHOR("Rob Clark <robdclark@gmail.com");
|
|
MODULE_DESCRIPTION("MSM DRM Driver");
|
|
MODULE_LICENSE("GPL");
|