mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-11-26 11:30:54 +07:00
347 lines
9.0 KiB
C
347 lines
9.0 KiB
C
/*
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* Copyright (C) 2007 Ben Skeggs.
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* All Rights Reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining
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* a copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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* distribute, sublicense, and/or sell copies of the Software, and to
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial
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* portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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* IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "drm.h"
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#include "nouveau_drv.h"
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#include "nouveau_dma.h"
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void
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nouveau_dma_pre_init(struct nouveau_channel *chan)
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{
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struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
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struct nouveau_bo *pushbuf = chan->pushbuf_bo;
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if (dev_priv->card_type == NV_50) {
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const int ib_size = pushbuf->bo.mem.size / 2;
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chan->dma.ib_base = (pushbuf->bo.mem.size - ib_size) >> 2;
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chan->dma.ib_max = (ib_size / 8) - 1;
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chan->dma.ib_put = 0;
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chan->dma.ib_free = chan->dma.ib_max - chan->dma.ib_put;
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chan->dma.max = (pushbuf->bo.mem.size - ib_size) >> 2;
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} else {
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chan->dma.max = (pushbuf->bo.mem.size >> 2) - 2;
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}
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chan->dma.put = 0;
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chan->dma.cur = chan->dma.put;
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chan->dma.free = chan->dma.max - chan->dma.cur;
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}
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int
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nouveau_dma_init(struct nouveau_channel *chan)
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{
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struct drm_device *dev = chan->dev;
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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struct nouveau_gpuobj *m2mf = NULL;
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struct nouveau_gpuobj *nvsw = NULL;
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int ret, i;
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/* Create NV_MEMORY_TO_MEMORY_FORMAT for buffer moves */
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ret = nouveau_gpuobj_gr_new(chan, dev_priv->card_type < NV_50 ?
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0x0039 : 0x5039, &m2mf);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_ref_add(dev, chan, NvM2MF, m2mf, NULL);
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if (ret)
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return ret;
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/* Create an NV_SW object for various sync purposes */
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ret = nouveau_gpuobj_sw_new(chan, NV_SW, &nvsw);
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if (ret)
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return ret;
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ret = nouveau_gpuobj_ref_add(dev, chan, NvSw, nvsw, NULL);
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if (ret)
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return ret;
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/* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
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ret = nouveau_notifier_alloc(chan, NvNotify0, 32, &chan->m2mf_ntfy);
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if (ret)
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return ret;
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/* Map push buffer */
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ret = nouveau_bo_map(chan->pushbuf_bo);
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if (ret)
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return ret;
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/* Insert NOPS for NOUVEAU_DMA_SKIPS */
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ret = RING_SPACE(chan, NOUVEAU_DMA_SKIPS);
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if (ret)
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return ret;
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for (i = 0; i < NOUVEAU_DMA_SKIPS; i++)
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OUT_RING(chan, 0);
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/* Initialise NV_MEMORY_TO_MEMORY_FORMAT */
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ret = RING_SPACE(chan, 4);
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if (ret)
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return ret;
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BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_NAME, 1);
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OUT_RING(chan, NvM2MF);
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BEGIN_RING(chan, NvSubM2MF, NV_MEMORY_TO_MEMORY_FORMAT_DMA_NOTIFY, 1);
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OUT_RING(chan, NvNotify0);
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/* Initialise NV_SW */
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ret = RING_SPACE(chan, 2);
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if (ret)
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return ret;
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BEGIN_RING(chan, NvSubSw, 0, 1);
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OUT_RING(chan, NvSw);
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/* Sit back and pray the channel works.. */
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FIRE_RING(chan);
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return 0;
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}
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void
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OUT_RINGp(struct nouveau_channel *chan, const void *data, unsigned nr_dwords)
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{
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bool is_iomem;
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u32 *mem = ttm_kmap_obj_virtual(&chan->pushbuf_bo->kmap, &is_iomem);
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mem = &mem[chan->dma.cur];
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if (is_iomem)
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memcpy_toio((void __force __iomem *)mem, data, nr_dwords * 4);
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else
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memcpy(mem, data, nr_dwords * 4);
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chan->dma.cur += nr_dwords;
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}
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/* Fetch and adjust GPU GET pointer
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*
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* Returns:
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* value >= 0, the adjusted GET pointer
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* -EINVAL if GET pointer currently outside main push buffer
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* -EBUSY if timeout exceeded
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*/
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static inline int
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READ_GET(struct nouveau_channel *chan, uint32_t *prev_get, uint32_t *timeout)
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{
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uint32_t val;
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val = nvchan_rd32(chan, chan->user_get);
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/* reset counter as long as GET is still advancing, this is
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* to avoid misdetecting a GPU lockup if the GPU happens to
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* just be processing an operation that takes a long time
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*/
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if (val != *prev_get) {
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*prev_get = val;
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*timeout = 0;
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}
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if ((++*timeout & 0xff) == 0) {
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DRM_UDELAY(1);
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if (*timeout > 100000)
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return -EBUSY;
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}
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if (val < chan->pushbuf_base ||
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val > chan->pushbuf_base + (chan->dma.max << 2))
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return -EINVAL;
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return (val - chan->pushbuf_base) >> 2;
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}
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void
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nv50_dma_push(struct nouveau_channel *chan, struct nouveau_bo *bo,
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int delta, int length)
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{
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struct nouveau_bo *pb = chan->pushbuf_bo;
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uint64_t offset = bo->bo.offset + delta;
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int ip = (chan->dma.ib_put * 2) + chan->dma.ib_base;
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BUG_ON(chan->dma.ib_free < 1);
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nouveau_bo_wr32(pb, ip++, lower_32_bits(offset));
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nouveau_bo_wr32(pb, ip++, upper_32_bits(offset) | length << 8);
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chan->dma.ib_put = (chan->dma.ib_put + 1) & chan->dma.ib_max;
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DRM_MEMORYBARRIER();
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/* Flush writes. */
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nouveau_bo_rd32(pb, 0);
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nvchan_wr32(chan, 0x8c, chan->dma.ib_put);
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chan->dma.ib_free--;
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}
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static int
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nv50_dma_push_wait(struct nouveau_channel *chan, int count)
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{
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uint32_t cnt = 0, prev_get = 0;
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while (chan->dma.ib_free < count) {
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uint32_t get = nvchan_rd32(chan, 0x88);
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if (get != prev_get) {
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prev_get = get;
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cnt = 0;
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}
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if ((++cnt & 0xff) == 0) {
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DRM_UDELAY(1);
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if (cnt > 100000)
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return -EBUSY;
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}
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chan->dma.ib_free = get - chan->dma.ib_put;
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if (chan->dma.ib_free <= 0)
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chan->dma.ib_free += chan->dma.ib_max + 1;
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}
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return 0;
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}
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static int
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nv50_dma_wait(struct nouveau_channel *chan, int slots, int count)
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{
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uint32_t cnt = 0, prev_get = 0;
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int ret;
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ret = nv50_dma_push_wait(chan, slots + 1);
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if (unlikely(ret))
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return ret;
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while (chan->dma.free < count) {
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int get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get < 0)) {
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if (get == -EINVAL)
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continue;
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return get;
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}
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if (get <= chan->dma.cur) {
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chan->dma.free = chan->dma.max - chan->dma.cur;
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if (chan->dma.free >= count)
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break;
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FIRE_RING(chan);
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do {
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get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get < 0)) {
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if (get == -EINVAL)
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continue;
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return get;
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}
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} while (get == 0);
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chan->dma.cur = 0;
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chan->dma.put = 0;
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}
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chan->dma.free = get - chan->dma.cur - 1;
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}
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return 0;
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}
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int
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nouveau_dma_wait(struct nouveau_channel *chan, int slots, int size)
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{
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uint32_t prev_get = 0, cnt = 0;
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int get;
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if (chan->dma.ib_max)
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return nv50_dma_wait(chan, slots, size);
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while (chan->dma.free < size) {
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get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get == -EBUSY))
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return -EBUSY;
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/* loop until we have a usable GET pointer. the value
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* we read from the GPU may be outside the main ring if
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* PFIFO is processing a buffer called from the main ring,
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* discard these values until something sensible is seen.
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*
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* the other case we discard GET is while the GPU is fetching
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* from the SKIPS area, so the code below doesn't have to deal
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* with some fun corner cases.
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*/
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if (unlikely(get == -EINVAL) || get < NOUVEAU_DMA_SKIPS)
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continue;
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if (get <= chan->dma.cur) {
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/* engine is fetching behind us, or is completely
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* idle (GET == PUT) so we have free space up until
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* the end of the push buffer
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*
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* we can only hit that path once per call due to
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* looping back to the beginning of the push buffer,
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* we'll hit the fetching-ahead-of-us path from that
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* point on.
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*
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* the *one* exception to that rule is if we read
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* GET==PUT, in which case the below conditional will
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* always succeed and break us out of the wait loop.
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*/
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chan->dma.free = chan->dma.max - chan->dma.cur;
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if (chan->dma.free >= size)
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break;
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/* not enough space left at the end of the push buffer,
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* instruct the GPU to jump back to the start right
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* after processing the currently pending commands.
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*/
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OUT_RING(chan, chan->pushbuf_base | 0x20000000);
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/* wait for GET to depart from the skips area.
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* prevents writing GET==PUT and causing a race
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* condition that causes us to think the GPU is
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* idle when it's not.
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*/
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do {
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get = READ_GET(chan, &prev_get, &cnt);
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if (unlikely(get == -EBUSY))
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return -EBUSY;
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if (unlikely(get == -EINVAL))
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continue;
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} while (get <= NOUVEAU_DMA_SKIPS);
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WRITE_PUT(NOUVEAU_DMA_SKIPS);
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/* we're now submitting commands at the start of
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* the push buffer.
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*/
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chan->dma.cur =
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chan->dma.put = NOUVEAU_DMA_SKIPS;
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}
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/* engine fetching ahead of us, we have space up until the
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* current GET pointer. the "- 1" is to ensure there's
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* space left to emit a jump back to the beginning of the
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* push buffer if we require it. we can never get GET == PUT
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* here, so this is safe.
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*/
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chan->dma.free = get - chan->dma.cur - 1;
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}
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return 0;
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}
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