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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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b2c3e38a54
Re-engineer the LPAE TTBR setup code. Rather than passing some shifted address in order to fit in a CPU register, pass either a full physical address (in the case of r4, r5 for TTBR0) or a PFN (for TTBR1). This removes the ARCH_PGD_SHIFT hack, and the last dangerous user of cpu_set_ttbr() in the secondary CPU startup code path (which was there to re-set TTBR1 to the appropriate high physical address space on Keystone2.) Tested-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
154 lines
3.5 KiB
C
154 lines
3.5 KiB
C
/*
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* arch/arm/include/asm/proc-fns.h
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*
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* Copyright (C) 1997-1999 Russell King
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* Copyright (C) 2000 Deep Blue Solutions Ltd
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __ASM_PROCFNS_H
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#define __ASM_PROCFNS_H
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#ifdef __KERNEL__
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#include <asm/glue-proc.h>
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#include <asm/page.h>
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#ifndef __ASSEMBLY__
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struct mm_struct;
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/*
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* Don't change this structure - ASM code relies on it.
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*/
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extern struct processor {
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/* MISC
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* get data abort address/flags
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*/
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void (*_data_abort)(unsigned long pc);
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/*
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* Retrieve prefetch fault address
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*/
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unsigned long (*_prefetch_abort)(unsigned long lr);
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/*
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* Set up any processor specifics
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*/
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void (*_proc_init)(void);
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/*
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* Disable any processor specifics
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*/
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void (*_proc_fin)(void);
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/*
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* Special stuff for a reset
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*/
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void (*reset)(unsigned long addr) __attribute__((noreturn));
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/*
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* Idle the processor
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*/
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int (*_do_idle)(void);
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/*
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* Processor architecture specific
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*/
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/*
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* clean a virtual address range from the
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* D-cache without flushing the cache.
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*/
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void (*dcache_clean_area)(void *addr, int size);
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/*
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* Set the page table
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*/
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void (*switch_mm)(phys_addr_t pgd_phys, struct mm_struct *mm);
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/*
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* Set a possibly extended PTE. Non-extended PTEs should
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* ignore 'ext'.
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*/
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#ifdef CONFIG_ARM_LPAE
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void (*set_pte_ext)(pte_t *ptep, pte_t pte);
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#else
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void (*set_pte_ext)(pte_t *ptep, pte_t pte, unsigned int ext);
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#endif
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/* Suspend/resume */
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unsigned int suspend_size;
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void (*do_suspend)(void *);
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void (*do_resume)(void *);
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} processor;
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#ifndef MULTI_CPU
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extern void cpu_proc_init(void);
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extern void cpu_proc_fin(void);
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extern int cpu_do_idle(void);
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extern void cpu_dcache_clean_area(void *, int);
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extern void cpu_do_switch_mm(phys_addr_t pgd_phys, struct mm_struct *mm);
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#ifdef CONFIG_ARM_LPAE
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extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte);
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#else
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extern void cpu_set_pte_ext(pte_t *ptep, pte_t pte, unsigned int ext);
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#endif
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extern void cpu_reset(unsigned long addr) __attribute__((noreturn));
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/* These three are private to arch/arm/kernel/suspend.c */
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extern void cpu_do_suspend(void *);
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extern void cpu_do_resume(void *);
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#else
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#define cpu_proc_init processor._proc_init
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#define cpu_proc_fin processor._proc_fin
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#define cpu_reset processor.reset
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#define cpu_do_idle processor._do_idle
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#define cpu_dcache_clean_area processor.dcache_clean_area
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#define cpu_set_pte_ext processor.set_pte_ext
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#define cpu_do_switch_mm processor.switch_mm
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/* These three are private to arch/arm/kernel/suspend.c */
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#define cpu_do_suspend processor.do_suspend
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#define cpu_do_resume processor.do_resume
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#endif
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extern void cpu_resume(void);
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#include <asm/memory.h>
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#ifdef CONFIG_MMU
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#define cpu_switch_mm(pgd,mm) cpu_do_switch_mm(virt_to_phys(pgd),mm)
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#ifdef CONFIG_ARM_LPAE
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#define cpu_get_ttbr(nr) \
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({ \
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u64 ttbr; \
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__asm__("mrrc p15, " #nr ", %Q0, %R0, c2" \
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: "=r" (ttbr)); \
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ttbr; \
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})
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#define cpu_get_pgd() \
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({ \
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u64 pg = cpu_get_ttbr(0); \
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pg &= ~(PTRS_PER_PGD*sizeof(pgd_t)-1); \
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(pgd_t *)phys_to_virt(pg); \
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})
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#else
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#define cpu_get_pgd() \
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({ \
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unsigned long pg; \
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__asm__("mrc p15, 0, %0, c2, c0, 0" \
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: "=r" (pg) : : "cc"); \
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pg &= ~0x3fff; \
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(pgd_t *)phys_to_virt(pg); \
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})
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#endif
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#else /*!CONFIG_MMU */
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#define cpu_switch_mm(pgd,mm) { }
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* __ASM_PROCFNS_H */
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