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8e6d08e0a1
This patch introduces the SMP support for the OpenRISC architecture. The SMP architecture requires cores which have multi-core features which have been introduced a few years back including: - New SPRS SPR_COREID SPR_NUMCORES - Shadow SPRs - Atomic Instructions - Cache Coherency - A wired in IPI controller This patch adds all of the SMP specific changes to core infrastructure, it looks big but it needs to go all together as its hard to split this one up. Boot loader spinning of second cpu is not supported yet, it's assumed that Linux is booted straight after cpu reset. The bulk of these changes are trivial changes to refactor to use per cpu data structures throughout. The addition of the smp.c and changes in time.c are the changes. Some specific notes: MM changes ---------- The reason why this is created as an array, and not with DEFINE_PER_CPU is that doing it this way, we'll save a load in the tlb-miss handler (the load from __per_cpu_offset). TLB Flush --------- The SMP implementation of flush_tlb_* works by sending out a function-call IPI to all the non-local cpus by using the generic on_each_cpu() function. Currently, all flush_tlb_* functions will result in a flush_tlb_all(), which has always been the behaviour in the UP case. CPU INFO -------- This creates a per cpu cpuinfo struct and fills it out accordingly for each activated cpu. show_cpuinfo is also updated to reflect new version information in later versions of the spec. SMP API ------- This imitates the arm64 implementation by having a smp_cross_call callback that can be set by set_smp_cross_call to initiate an IPI and a handle_IPI function that is expected to be called from an IPI irqchip driver. Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi> [shorne@gmail.com: added cpu stop, checkpatch fixes, wrote commit message] Signed-off-by: Stafford Horne <shorne@gmail.com>
261 lines
6.6 KiB
C
261 lines
6.6 KiB
C
/*
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* OpenRISC Linux
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*
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* Linux architectural port borrowing liberally from similar works of
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* others. All original copyrights apply as per the original source
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* declaration.
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*
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* Modifications for the OpenRISC architecture:
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* Copyright (C) 2003 Matjaz Breskvar <phoenix@bsemi.com>
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* Copyright (C) 2010-2011 Jonas Bonn <jonas@southpole.se>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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* DMA mapping callbacks...
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* As alloc_coherent is the only DMA callback being used currently, that's
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* the only thing implemented properly. The rest need looking into...
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*/
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#include <linux/dma-mapping.h>
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#include <linux/dma-debug.h>
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#include <linux/export.h>
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#include <asm/cpuinfo.h>
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#include <asm/spr_defs.h>
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#include <asm/tlbflush.h>
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static int
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page_set_nocache(pte_t *pte, unsigned long addr,
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unsigned long next, struct mm_walk *walk)
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{
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unsigned long cl;
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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pte_val(*pte) |= _PAGE_CI;
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/*
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* Flush the page out of the TLB so that the new page flags get
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* picked up next time there's an access
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*/
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flush_tlb_page(NULL, addr);
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/* Flush page out of dcache */
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for (cl = __pa(addr); cl < __pa(next); cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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return 0;
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}
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static int
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page_clear_nocache(pte_t *pte, unsigned long addr,
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unsigned long next, struct mm_walk *walk)
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{
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pte_val(*pte) &= ~_PAGE_CI;
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/*
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* Flush the page out of the TLB so that the new page flags get
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* picked up next time there's an access
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*/
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flush_tlb_page(NULL, addr);
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return 0;
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}
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/*
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* Alloc "coherent" memory, which for OpenRISC means simply uncached.
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*
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* This function effectively just calls __get_free_pages, sets the
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* cache-inhibit bit on those pages, and makes sure that the pages are
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* flushed out of the cache before they are used.
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*
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* If the NON_CONSISTENT attribute is set, then this function just
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* returns "normal", cachable memory.
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*
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* There are additional flags WEAK_ORDERING and WRITE_COMBINE to take
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* into consideration here, too. All current known implementations of
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* the OR1K support only strongly ordered memory accesses, so that flag
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* is being ignored for now; uncached but write-combined memory is a
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* missing feature of the OR1K.
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*/
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static void *
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or1k_dma_alloc(struct device *dev, size_t size,
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dma_addr_t *dma_handle, gfp_t gfp,
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unsigned long attrs)
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{
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unsigned long va;
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void *page;
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struct mm_walk walk = {
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.pte_entry = page_set_nocache,
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.mm = &init_mm
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};
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page = alloc_pages_exact(size, gfp);
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if (!page)
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return NULL;
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/* This gives us the real physical address of the first page. */
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*dma_handle = __pa(page);
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va = (unsigned long)page;
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if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
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/*
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* We need to iterate through the pages, clearing the dcache for
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* them and setting the cache-inhibit bit.
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*/
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if (walk_page_range(va, va + size, &walk)) {
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free_pages_exact(page, size);
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return NULL;
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}
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}
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return (void *)va;
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}
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static void
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or1k_dma_free(struct device *dev, size_t size, void *vaddr,
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dma_addr_t dma_handle, unsigned long attrs)
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{
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unsigned long va = (unsigned long)vaddr;
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struct mm_walk walk = {
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.pte_entry = page_clear_nocache,
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.mm = &init_mm
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};
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if ((attrs & DMA_ATTR_NON_CONSISTENT) == 0) {
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/* walk_page_range shouldn't be able to fail here */
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WARN_ON(walk_page_range(va, va + size, &walk));
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}
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free_pages_exact(vaddr, size);
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}
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static dma_addr_t
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or1k_map_page(struct device *dev, struct page *page,
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unsigned long offset, size_t size,
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enum dma_data_direction dir,
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unsigned long attrs)
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{
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unsigned long cl;
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dma_addr_t addr = page_to_phys(page) + offset;
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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if (attrs & DMA_ATTR_SKIP_CPU_SYNC)
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return addr;
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switch (dir) {
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case DMA_TO_DEVICE:
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/* Flush the dcache for the requested range */
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for (cl = addr; cl < addr + size;
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cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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break;
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case DMA_FROM_DEVICE:
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/* Invalidate the dcache for the requested range */
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for (cl = addr; cl < addr + size;
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cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBIR, cl);
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break;
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default:
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/*
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* NOTE: If dir == DMA_BIDIRECTIONAL then there's no need to
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* flush nor invalidate the cache here as the area will need
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* to be manually synced anyway.
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*/
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break;
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}
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return addr;
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}
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static void
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or1k_unmap_page(struct device *dev, dma_addr_t dma_handle,
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size_t size, enum dma_data_direction dir,
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unsigned long attrs)
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{
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/* Nothing special to do here... */
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}
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static int
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or1k_map_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct scatterlist *s;
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int i;
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for_each_sg(sg, s, nents, i) {
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s->dma_address = or1k_map_page(dev, sg_page(s), s->offset,
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s->length, dir, 0);
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}
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return nents;
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}
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static void
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or1k_unmap_sg(struct device *dev, struct scatterlist *sg,
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int nents, enum dma_data_direction dir,
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unsigned long attrs)
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{
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struct scatterlist *s;
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int i;
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for_each_sg(sg, s, nents, i) {
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or1k_unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, 0);
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}
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}
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static void
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or1k_sync_single_for_cpu(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long cl;
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dma_addr_t addr = dma_handle;
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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/* Invalidate the dcache for the requested range */
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for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBIR, cl);
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}
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static void
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or1k_sync_single_for_device(struct device *dev,
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dma_addr_t dma_handle, size_t size,
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enum dma_data_direction dir)
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{
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unsigned long cl;
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dma_addr_t addr = dma_handle;
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struct cpuinfo_or1k *cpuinfo = &cpuinfo_or1k[smp_processor_id()];
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/* Flush the dcache for the requested range */
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for (cl = addr; cl < addr + size; cl += cpuinfo->dcache_block_size)
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mtspr(SPR_DCBFR, cl);
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}
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const struct dma_map_ops or1k_dma_map_ops = {
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.alloc = or1k_dma_alloc,
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.free = or1k_dma_free,
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.map_page = or1k_map_page,
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.unmap_page = or1k_unmap_page,
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.map_sg = or1k_map_sg,
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.unmap_sg = or1k_unmap_sg,
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.sync_single_for_cpu = or1k_sync_single_for_cpu,
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.sync_single_for_device = or1k_sync_single_for_device,
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};
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EXPORT_SYMBOL(or1k_dma_map_ops);
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/* Number of entries preallocated for DMA-API debugging */
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#define PREALLOC_DMA_DEBUG_ENTRIES (1 << 16)
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static int __init dma_init(void)
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{
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dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
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return 0;
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}
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fs_initcall(dma_init);
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