mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-27 10:15:10 +07:00
8067302973
The ethernet core has 3 IRQs. Using the IRQ grouping registers we are able to separate TX and RX IRQs, which allows us to service them on separate cores. This patch splits the IRQ handler into 2 separate functions, one for TX and another for RX. The TX housekeeping is split out into its own NAPI handler. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: David S. Miller <davem@davemloft.net>
437 lines
13 KiB
C
437 lines
13 KiB
C
/* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* Copyright (C) 2009-2016 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2009-2016 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2013-2016 Michael Lee <igvtee@gmail.com>
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*/
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#ifndef MTK_ETH_H
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#define MTK_ETH_H
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#define MTK_QDMA_PAGE_SIZE 2048
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#define MTK_MAX_RX_LENGTH 1536
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#define MTK_TX_DMA_BUF_LEN 0x3fff
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#define MTK_DMA_SIZE 256
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#define MTK_NAPI_WEIGHT 64
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#define MTK_MAC_COUNT 2
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#define MTK_RX_ETH_HLEN (VLAN_ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN)
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#define MTK_RX_HLEN (NET_SKB_PAD + MTK_RX_ETH_HLEN + NET_IP_ALIGN)
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#define MTK_DMA_DUMMY_DESC 0xffffffff
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#define MTK_DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | \
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NETIF_MSG_PROBE | \
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NETIF_MSG_LINK | \
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NETIF_MSG_TIMER | \
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NETIF_MSG_IFDOWN | \
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NETIF_MSG_IFUP | \
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NETIF_MSG_RX_ERR | \
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NETIF_MSG_TX_ERR)
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#define MTK_HW_FEATURES (NETIF_F_IP_CSUM | \
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NETIF_F_RXCSUM | \
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NETIF_F_HW_VLAN_CTAG_TX | \
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NETIF_F_HW_VLAN_CTAG_RX | \
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NETIF_F_SG | NETIF_F_TSO | \
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NETIF_F_TSO6 | \
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NETIF_F_IPV6_CSUM)
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#define NEXT_RX_DESP_IDX(X) (((X) + 1) & (MTK_DMA_SIZE - 1))
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/* Frame Engine Global Reset Register */
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#define MTK_RST_GL 0x04
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#define RST_GL_PSE BIT(0)
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/* Frame Engine Interrupt Status Register */
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#define MTK_INT_STATUS2 0x08
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#define MTK_GDM1_AF BIT(28)
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#define MTK_GDM2_AF BIT(29)
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/* Frame Engine Interrupt Grouping Register */
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#define MTK_FE_INT_GRP 0x20
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/* CDMP Exgress Control Register */
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#define MTK_CDMP_EG_CTRL 0x404
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/* GDM Exgress Control Register */
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#define MTK_GDMA_FWD_CFG(x) (0x500 + (x * 0x1000))
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#define MTK_GDMA_ICS_EN BIT(22)
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#define MTK_GDMA_TCS_EN BIT(21)
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#define MTK_GDMA_UCS_EN BIT(20)
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/* Unicast Filter MAC Address Register - Low */
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#define MTK_GDMA_MAC_ADRL(x) (0x508 + (x * 0x1000))
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/* Unicast Filter MAC Address Register - High */
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#define MTK_GDMA_MAC_ADRH(x) (0x50C + (x * 0x1000))
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/* PDMA Interrupt grouping registers */
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#define MTK_PDMA_INT_GRP1 0xa50
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#define MTK_PDMA_INT_GRP2 0xa54
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/* QDMA TX Queue Configuration Registers */
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#define MTK_QTX_CFG(x) (0x1800 + (x * 0x10))
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#define QDMA_RES_THRES 4
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/* QDMA TX Queue Scheduler Registers */
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#define MTK_QTX_SCH(x) (0x1804 + (x * 0x10))
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/* QDMA RX Base Pointer Register */
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#define MTK_QRX_BASE_PTR0 0x1900
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/* QDMA RX Maximum Count Register */
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#define MTK_QRX_MAX_CNT0 0x1904
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/* QDMA RX CPU Pointer Register */
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#define MTK_QRX_CRX_IDX0 0x1908
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/* QDMA RX DMA Pointer Register */
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#define MTK_QRX_DRX_IDX0 0x190C
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/* QDMA Global Configuration Register */
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#define MTK_QDMA_GLO_CFG 0x1A04
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#define MTK_RX_2B_OFFSET BIT(31)
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#define MTK_RX_BT_32DWORDS (3 << 11)
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#define MTK_NDP_CO_PRO BIT(10)
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#define MTK_TX_WB_DDONE BIT(6)
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#define MTK_DMA_SIZE_16DWORDS (2 << 4)
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#define MTK_RX_DMA_BUSY BIT(3)
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#define MTK_TX_DMA_BUSY BIT(1)
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#define MTK_RX_DMA_EN BIT(2)
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#define MTK_TX_DMA_EN BIT(0)
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#define MTK_DMA_BUSY_TIMEOUT HZ
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/* QDMA Reset Index Register */
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#define MTK_QDMA_RST_IDX 0x1A08
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#define MTK_PST_DRX_IDX0 BIT(16)
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/* QDMA Delay Interrupt Register */
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#define MTK_QDMA_DELAY_INT 0x1A0C
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/* QDMA Flow Control Register */
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#define MTK_QDMA_FC_THRES 0x1A10
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#define FC_THRES_DROP_MODE BIT(20)
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#define FC_THRES_DROP_EN (7 << 16)
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#define FC_THRES_MIN 0x4444
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/* QDMA Interrupt Status Register */
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#define MTK_QMTK_INT_STATUS 0x1A18
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#define MTK_RX_DONE_INT1 BIT(17)
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#define MTK_RX_DONE_INT0 BIT(16)
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#define MTK_TX_DONE_INT3 BIT(3)
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#define MTK_TX_DONE_INT2 BIT(2)
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#define MTK_TX_DONE_INT1 BIT(1)
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#define MTK_TX_DONE_INT0 BIT(0)
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#define MTK_RX_DONE_INT (MTK_RX_DONE_INT0 | MTK_RX_DONE_INT1)
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#define MTK_TX_DONE_INT (MTK_TX_DONE_INT0 | MTK_TX_DONE_INT1 | \
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MTK_TX_DONE_INT2 | MTK_TX_DONE_INT3)
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/* QDMA Interrupt grouping registers */
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#define MTK_QDMA_INT_GRP1 0x1a20
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#define MTK_QDMA_INT_GRP2 0x1a24
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#define MTK_RLS_DONE_INT BIT(0)
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/* QDMA Interrupt Status Register */
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#define MTK_QDMA_INT_MASK 0x1A1C
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/* QDMA Interrupt Mask Register */
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#define MTK_QDMA_HRED2 0x1A44
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/* QDMA TX Forward CPU Pointer Register */
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#define MTK_QTX_CTX_PTR 0x1B00
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/* QDMA TX Forward DMA Pointer Register */
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#define MTK_QTX_DTX_PTR 0x1B04
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/* QDMA TX Release CPU Pointer Register */
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#define MTK_QTX_CRX_PTR 0x1B10
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/* QDMA TX Release DMA Pointer Register */
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#define MTK_QTX_DRX_PTR 0x1B14
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/* QDMA FQ Head Pointer Register */
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#define MTK_QDMA_FQ_HEAD 0x1B20
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/* QDMA FQ Head Pointer Register */
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#define MTK_QDMA_FQ_TAIL 0x1B24
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/* QDMA FQ Free Page Counter Register */
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#define MTK_QDMA_FQ_CNT 0x1B28
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/* QDMA FQ Free Page Buffer Length Register */
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#define MTK_QDMA_FQ_BLEN 0x1B2C
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/* GMA1 Received Good Byte Count Register */
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#define MTK_GDM1_TX_GBCNT 0x2400
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#define MTK_STAT_OFFSET 0x40
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/* QDMA descriptor txd4 */
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#define TX_DMA_CHKSUM (0x7 << 29)
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#define TX_DMA_TSO BIT(28)
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#define TX_DMA_FPORT_SHIFT 25
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#define TX_DMA_FPORT_MASK 0x7
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#define TX_DMA_INS_VLAN BIT(16)
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/* QDMA descriptor txd3 */
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#define TX_DMA_OWNER_CPU BIT(31)
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#define TX_DMA_LS0 BIT(30)
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#define TX_DMA_PLEN0(_x) (((_x) & MTK_TX_DMA_BUF_LEN) << 16)
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#define TX_DMA_SWC BIT(14)
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#define TX_DMA_SDL(_x) (((_x) & 0x3fff) << 16)
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/* QDMA descriptor rxd2 */
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#define RX_DMA_DONE BIT(31)
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#define RX_DMA_PLEN0(_x) (((_x) & 0x3fff) << 16)
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#define RX_DMA_GET_PLEN0(_x) (((_x) >> 16) & 0x3fff)
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/* QDMA descriptor rxd3 */
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#define RX_DMA_VID(_x) ((_x) & 0xfff)
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/* QDMA descriptor rxd4 */
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#define RX_DMA_L4_VALID BIT(24)
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#define RX_DMA_FPORT_SHIFT 19
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#define RX_DMA_FPORT_MASK 0x7
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/* PHY Indirect Access Control registers */
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#define MTK_PHY_IAC 0x10004
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#define PHY_IAC_ACCESS BIT(31)
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#define PHY_IAC_READ BIT(19)
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#define PHY_IAC_WRITE BIT(18)
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#define PHY_IAC_START BIT(16)
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#define PHY_IAC_ADDR_SHIFT 20
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#define PHY_IAC_REG_SHIFT 25
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#define PHY_IAC_TIMEOUT HZ
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/* Mac control registers */
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#define MTK_MAC_MCR(x) (0x10100 + (x * 0x100))
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#define MAC_MCR_MAX_RX_1536 BIT(24)
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#define MAC_MCR_IPG_CFG (BIT(18) | BIT(16))
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#define MAC_MCR_FORCE_MODE BIT(15)
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#define MAC_MCR_TX_EN BIT(14)
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#define MAC_MCR_RX_EN BIT(13)
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#define MAC_MCR_BACKOFF_EN BIT(9)
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#define MAC_MCR_BACKPR_EN BIT(8)
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#define MAC_MCR_FORCE_RX_FC BIT(5)
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#define MAC_MCR_FORCE_TX_FC BIT(4)
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#define MAC_MCR_SPEED_1000 BIT(3)
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#define MAC_MCR_SPEED_100 BIT(2)
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#define MAC_MCR_FORCE_DPX BIT(1)
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#define MAC_MCR_FORCE_LINK BIT(0)
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#define MAC_MCR_FIXED_LINK (MAC_MCR_MAX_RX_1536 | MAC_MCR_IPG_CFG | \
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MAC_MCR_FORCE_MODE | MAC_MCR_TX_EN | \
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MAC_MCR_RX_EN | MAC_MCR_BACKOFF_EN | \
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MAC_MCR_BACKPR_EN | MAC_MCR_FORCE_RX_FC | \
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MAC_MCR_FORCE_TX_FC | MAC_MCR_SPEED_1000 | \
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MAC_MCR_FORCE_DPX | MAC_MCR_FORCE_LINK)
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/* GPIO port control registers for GMAC 2*/
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#define GPIO_OD33_CTRL8 0x4c0
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#define GPIO_BIAS_CTRL 0xed0
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#define GPIO_DRV_SEL10 0xf00
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/* ethernet subsystem config register */
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#define ETHSYS_SYSCFG0 0x14
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#define SYSCFG0_GE_MASK 0x3
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#define SYSCFG0_GE_MODE(x, y) (x << (12 + (y * 2)))
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struct mtk_rx_dma {
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unsigned int rxd1;
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unsigned int rxd2;
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unsigned int rxd3;
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unsigned int rxd4;
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} __packed __aligned(4);
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struct mtk_tx_dma {
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unsigned int txd1;
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unsigned int txd2;
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unsigned int txd3;
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unsigned int txd4;
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} __packed __aligned(4);
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struct mtk_eth;
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struct mtk_mac;
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/* struct mtk_hw_stats - the structure that holds the traffic statistics.
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* @stats_lock: make sure that stats operations are atomic
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* @reg_offset: the status register offset of the SoC
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* @syncp: the refcount
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*
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* All of the supported SoCs have hardware counters for traffic statistics.
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* Whenever the status IRQ triggers we can read the latest stats from these
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* counters and store them in this struct.
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*/
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struct mtk_hw_stats {
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u64 tx_bytes;
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u64 tx_packets;
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u64 tx_skip;
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u64 tx_collisions;
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u64 rx_bytes;
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u64 rx_packets;
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u64 rx_overflow;
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u64 rx_fcs_errors;
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u64 rx_short_errors;
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u64 rx_long_errors;
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u64 rx_checksum_errors;
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u64 rx_flow_control_packets;
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spinlock_t stats_lock;
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u32 reg_offset;
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struct u64_stats_sync syncp;
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};
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/* PDMA descriptor can point at 1-2 segments. This enum allows us to track how
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* memory was allocated so that it can be freed properly
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*/
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enum mtk_tx_flags {
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MTK_TX_FLAGS_SINGLE0 = 0x01,
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MTK_TX_FLAGS_PAGE0 = 0x02,
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};
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/* struct mtk_tx_buf - This struct holds the pointers to the memory pointed at
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* by the TX descriptor s
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* @skb: The SKB pointer of the packet being sent
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* @dma_addr0: The base addr of the first segment
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* @dma_len0: The length of the first segment
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* @dma_addr1: The base addr of the second segment
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* @dma_len1: The length of the second segment
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*/
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struct mtk_tx_buf {
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struct sk_buff *skb;
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u32 flags;
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DEFINE_DMA_UNMAP_ADDR(dma_addr0);
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DEFINE_DMA_UNMAP_LEN(dma_len0);
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DEFINE_DMA_UNMAP_ADDR(dma_addr1);
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DEFINE_DMA_UNMAP_LEN(dma_len1);
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};
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/* struct mtk_tx_ring - This struct holds info describing a TX ring
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* @dma: The descriptor ring
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* @buf: The memory pointed at by the ring
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* @phys: The physical addr of tx_buf
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* @next_free: Pointer to the next free descriptor
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* @last_free: Pointer to the last free descriptor
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* @thresh: The threshold of minimum amount of free descriptors
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* @free_count: QDMA uses a linked list. Track how many free descriptors
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* are present
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*/
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struct mtk_tx_ring {
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struct mtk_tx_dma *dma;
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struct mtk_tx_buf *buf;
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dma_addr_t phys;
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struct mtk_tx_dma *next_free;
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struct mtk_tx_dma *last_free;
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u16 thresh;
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atomic_t free_count;
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};
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/* struct mtk_rx_ring - This struct holds info describing a RX ring
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* @dma: The descriptor ring
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* @data: The memory pointed at by the ring
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* @phys: The physical addr of rx_buf
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* @frag_size: How big can each fragment be
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* @buf_size: The size of each packet buffer
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* @calc_idx: The current head of ring
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*/
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struct mtk_rx_ring {
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struct mtk_rx_dma *dma;
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u8 **data;
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dma_addr_t phys;
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u16 frag_size;
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u16 buf_size;
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u16 calc_idx;
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};
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/* currently no SoC has more than 2 macs */
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#define MTK_MAX_DEVS 2
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/* struct mtk_eth - This is the main datasructure for holding the state
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* of the driver
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* @dev: The device pointer
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* @base: The mapped register i/o base
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* @page_lock: Make sure that register operations are atomic
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* @dummy_dev: we run 2 netdevs on 1 physical DMA ring and need a
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* dummy for NAPI to work
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* @netdev: The netdev instances
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* @mac: Each netdev is linked to a physical MAC
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* @irq: The IRQ that we are using
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* @msg_enable: Ethtool msg level
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* @ethsys: The register map pointing at the range used to setup
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* MII modes
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* @pctl: The register map pointing at the range used to setup
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* GMAC port drive/slew values
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* @dma_refcnt: track how many netdevs are using the DMA engine
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* @tx_ring: Pointer to the memore holding info about the TX ring
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* @rx_ring: Pointer to the memore holding info about the RX ring
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* @tx_napi: The TX NAPI struct
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* @rx_napi: The RX NAPI struct
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* @scratch_ring: Newer SoCs need memory for a second HW managed TX ring
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* @phy_scratch_ring: physical address of scratch_ring
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* @scratch_head: The scratch memory that scratch_ring points to.
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* @clk_ethif: The ethif clock
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* @clk_esw: The switch clock
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* @clk_gp1: The gmac1 clock
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* @clk_gp2: The gmac2 clock
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* @mii_bus: If there is a bus we need to create an instance for it
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* @pending_work: The workqueue used to reset the dma ring
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*/
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struct mtk_eth {
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struct device *dev;
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void __iomem *base;
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struct reset_control *rstc;
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spinlock_t page_lock;
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spinlock_t irq_lock;
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struct net_device dummy_dev;
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struct net_device *netdev[MTK_MAX_DEVS];
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struct mtk_mac *mac[MTK_MAX_DEVS];
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int irq[3];
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u32 msg_enable;
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unsigned long sysclk;
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struct regmap *ethsys;
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struct regmap *pctl;
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atomic_t dma_refcnt;
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struct mtk_tx_ring tx_ring;
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struct mtk_rx_ring rx_ring;
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struct napi_struct tx_napi;
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struct napi_struct rx_napi;
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struct mtk_tx_dma *scratch_ring;
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dma_addr_t phy_scratch_ring;
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void *scratch_head;
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struct clk *clk_ethif;
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struct clk *clk_esw;
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struct clk *clk_gp1;
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struct clk *clk_gp2;
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struct mii_bus *mii_bus;
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struct work_struct pending_work;
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};
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/* struct mtk_mac - the structure that holds the info about the MACs of the
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* SoC
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* @id: The number of the MAC
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* @of_node: Our devicetree node
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* @hw: Backpointer to our main datastruture
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* @hw_stats: Packet statistics counter
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* @phy_dev: The attached PHY if available
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*/
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struct mtk_mac {
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int id;
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struct device_node *of_node;
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struct mtk_eth *hw;
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struct mtk_hw_stats *hw_stats;
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struct phy_device *phy_dev;
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};
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/* the struct describing the SoC. these are declared in the soc_xyz.c files */
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extern const struct of_device_id of_mtk_match[];
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/* read the hardware status register */
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void mtk_stats_update_mac(struct mtk_mac *mac);
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void mtk_w32(struct mtk_eth *eth, u32 val, unsigned reg);
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u32 mtk_r32(struct mtk_eth *eth, unsigned reg);
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#endif /* MTK_ETH_H */
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