mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-26 20:35:24 +07:00
d947075739
Chandan reported that fstests' generic/026 test hit a crash:
BUG: Unable to handle kernel data access at 0xc00000062ac40000
Faulting instruction address: 0xc000000000092240
Oops: Kernel access of bad area, sig: 11 [#1]
LE SMP NR_CPUS=2048 DEBUG_PAGEALLOC NUMA pSeries
CPU: 0 PID: 27828 Comm: chacl Not tainted 5.0.0-rc2-next-20190115-00001-g6de6dba64dda #1
NIP: c000000000092240 LR: c00000000066a55c CTR: 0000000000000000
REGS: c00000062c0c3430 TRAP: 0300 Not tainted (5.0.0-rc2-next-20190115-00001-g6de6dba64dda)
MSR: 8000000002009033 <SF,VEC,EE,ME,IR,DR,RI,LE> CR: 44000842 XER: 20000000
CFAR: 00007fff7f3108ac DAR: c00000062ac40000 DSISR: 40000000 IRQMASK: 0
GPR00: 0000000000000000 c00000062c0c36c0 c0000000017f4c00 c00000000121a660
GPR04: c00000062ac3fff9 0000000000000004 0000000000000020 00000000275b19c4
GPR08: 000000000000000c 46494c4500000000 5347495f41434c5f c0000000026073a0
GPR12: 0000000000000000 c0000000027a0000 0000000000000000 0000000000000000
GPR16: 0000000000000000 0000000000000000 0000000000000000 0000000000000000
GPR20: c00000062ea70020 c00000062c0c38d0 0000000000000002 0000000000000002
GPR24: c00000062ac3ffe8 00000000275b19c4 0000000000000001 c00000062ac30000
GPR28: c00000062c0c38d0 c00000062ac30050 c00000062ac30058 0000000000000000
NIP memcmp+0x120/0x690
LR xfs_attr3_leaf_lookup_int+0x53c/0x5b0
Call Trace:
xfs_attr3_leaf_lookup_int+0x78/0x5b0 (unreliable)
xfs_da3_node_lookup_int+0x32c/0x5a0
xfs_attr_node_addname+0x170/0x6b0
xfs_attr_set+0x2ac/0x340
__xfs_set_acl+0xf0/0x230
xfs_set_acl+0xd0/0x160
set_posix_acl+0xc0/0x130
posix_acl_xattr_set+0x68/0x110
__vfs_setxattr+0xa4/0x110
__vfs_setxattr_noperm+0xac/0x240
vfs_setxattr+0x128/0x130
setxattr+0x248/0x600
path_setxattr+0x108/0x120
sys_setxattr+0x28/0x40
system_call+0x5c/0x70
Instruction dump:
7d201c28 7d402428 7c295040 38630008 38840008 408201f0 4200ffe8 2c050000
4182ff6c 20c50008 54c61838 7d201c28 <7d402428> 7d293436 7d4a3436 7c295040
The instruction dump decodes as:
subfic r6,r5,8
rlwinm r6,r6,3,0,28
ldbrx r9,0,r3
ldbrx r10,0,r4 <-
Which shows us doing an 8 byte load from c00000062ac3fff9, which
crosses the page boundary at c00000062ac40000 and faults.
It's not OK for memcmp to read past the end of the source or
destination buffers if that would cross a page boundary, because we
don't know that the next page is mapped.
As pointed out by Segher, we can read past the end of the source or
destination as long as we don't cross a 4K boundary, because that's
our minimum page size on all platforms.
The bug is in the code at the .Lcmp_rest_lt8bytes label. When we get
there we know that s1 is 8-byte aligned and we have at least 1 byte to
read, so a single 8-byte load won't read past the end of s1 and cross
a page boundary.
But we have to be more careful with s2. So check if it's within 8
bytes of a 4K boundary and if so go to the byte-by-byte loop.
Fixes: 2d9ee327ad ("powerpc/64: Align bytes before fall back to .Lshort in powerpc64 memcmp()")
Cc: stable@vger.kernel.org # v4.19+
Reported-by: Chandan Rajendra <chandan@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Reviewed-by: Segher Boessenkool <segher@kernel.crashing.org>
Tested-by: Chandan Rajendra <chandan@linux.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
643 lines
12 KiB
ArmAsm
643 lines
12 KiB
ArmAsm
/*
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* Author: Anton Blanchard <anton@au.ibm.com>
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* Copyright 2015 IBM Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#include <asm/ppc_asm.h>
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#include <asm/export.h>
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#include <asm/ppc-opcode.h>
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#define off8 r6
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#define off16 r7
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#define off24 r8
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#define rA r9
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#define rB r10
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#define rC r11
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#define rD r27
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#define rE r28
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#define rF r29
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#define rG r30
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#define rH r31
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#ifdef __LITTLE_ENDIAN__
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#define LH lhbrx
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#define LW lwbrx
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#define LD ldbrx
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#define LVS lvsr
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#define VPERM(_VRT,_VRA,_VRB,_VRC) \
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vperm _VRT,_VRB,_VRA,_VRC
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#else
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#define LH lhzx
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#define LW lwzx
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#define LD ldx
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#define LVS lvsl
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#define VPERM(_VRT,_VRA,_VRB,_VRC) \
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vperm _VRT,_VRA,_VRB,_VRC
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#endif
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#define VMX_THRESH 4096
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#define ENTER_VMX_OPS \
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mflr r0; \
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std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
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std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
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std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
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std r0,16(r1); \
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stdu r1,-STACKFRAMESIZE(r1); \
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bl enter_vmx_ops; \
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cmpwi cr1,r3,0; \
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ld r0,STACKFRAMESIZE+16(r1); \
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ld r3,STK_REG(R31)(r1); \
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ld r4,STK_REG(R30)(r1); \
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ld r5,STK_REG(R29)(r1); \
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addi r1,r1,STACKFRAMESIZE; \
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mtlr r0
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#define EXIT_VMX_OPS \
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mflr r0; \
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std r3,-STACKFRAMESIZE+STK_REG(R31)(r1); \
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std r4,-STACKFRAMESIZE+STK_REG(R30)(r1); \
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std r5,-STACKFRAMESIZE+STK_REG(R29)(r1); \
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std r0,16(r1); \
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stdu r1,-STACKFRAMESIZE(r1); \
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bl exit_vmx_ops; \
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ld r0,STACKFRAMESIZE+16(r1); \
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ld r3,STK_REG(R31)(r1); \
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ld r4,STK_REG(R30)(r1); \
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ld r5,STK_REG(R29)(r1); \
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addi r1,r1,STACKFRAMESIZE; \
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mtlr r0
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/*
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* LD_VSR_CROSS16B load the 2nd 16 bytes for _vaddr which is unaligned with
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* 16 bytes boundary and permute the result with the 1st 16 bytes.
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* | y y y y y y y y y y y y y 0 1 2 | 3 4 5 6 7 8 9 a b c d e f z z z |
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* ^ ^ ^
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* 0xbbbb10 0xbbbb20 0xbbb30
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* ^
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* _vaddr
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*
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*
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* _vmask is the mask generated by LVS
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* _v1st_qw is the 1st aligned QW of current addr which is already loaded.
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* for example: 0xyyyyyyyyyyyyy012 for big endian
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* _v2nd_qw is the 2nd aligned QW of cur _vaddr to be loaded.
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* for example: 0x3456789abcdefzzz for big endian
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* The permute result is saved in _v_res.
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* for example: 0x0123456789abcdef for big endian.
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*/
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#define LD_VSR_CROSS16B(_vaddr,_vmask,_v1st_qw,_v2nd_qw,_v_res) \
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lvx _v2nd_qw,_vaddr,off16; \
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VPERM(_v_res,_v1st_qw,_v2nd_qw,_vmask)
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/*
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* There are 2 categories for memcmp:
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* 1) src/dst has the same offset to the 8 bytes boundary. The handlers
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* are named like .Lsameoffset_xxxx
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* 2) src/dst has different offset to the 8 bytes boundary. The handlers
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* are named like .Ldiffoffset_xxxx
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*/
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_GLOBAL_TOC(memcmp)
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cmpdi cr1,r5,0
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/* Use the short loop if the src/dst addresses are not
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* with the same offset of 8 bytes align boundary.
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*/
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xor r6,r3,r4
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andi. r6,r6,7
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/* Fall back to short loop if compare at aligned addrs
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* with less than 8 bytes.
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*/
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cmpdi cr6,r5,7
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beq cr1,.Lzero
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bgt cr6,.Lno_short
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.Lshort:
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mtctr r5
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1: lbz rA,0(r3)
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lbz rB,0(r4)
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subf. rC,rB,rA
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bne .Lnon_zero
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bdz .Lzero
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lbz rA,1(r3)
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lbz rB,1(r4)
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subf. rC,rB,rA
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bne .Lnon_zero
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bdz .Lzero
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lbz rA,2(r3)
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lbz rB,2(r4)
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subf. rC,rB,rA
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bne .Lnon_zero
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bdz .Lzero
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lbz rA,3(r3)
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lbz rB,3(r4)
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subf. rC,rB,rA
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bne .Lnon_zero
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addi r3,r3,4
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addi r4,r4,4
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bdnz 1b
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.Lzero:
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li r3,0
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blr
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.Lno_short:
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dcbt 0,r3
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dcbt 0,r4
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bne .Ldiffoffset_8bytes_make_align_start
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.Lsameoffset_8bytes_make_align_start:
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/* attempt to compare bytes not aligned with 8 bytes so that
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* rest comparison can run based on 8 bytes alignment.
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*/
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andi. r6,r3,7
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/* Try to compare the first double word which is not 8 bytes aligned:
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* load the first double word at (src & ~7UL) and shift left appropriate
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* bits before comparision.
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*/
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rlwinm r6,r3,3,26,28
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beq .Lsameoffset_8bytes_aligned
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clrrdi r3,r3,3
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clrrdi r4,r4,3
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LD rA,0,r3
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LD rB,0,r4
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sld rA,rA,r6
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sld rB,rB,r6
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cmpld cr0,rA,rB
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srwi r6,r6,3
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bne cr0,.LcmpAB_lightweight
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subfic r6,r6,8
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subf. r5,r6,r5
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addi r3,r3,8
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addi r4,r4,8
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beq .Lzero
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.Lsameoffset_8bytes_aligned:
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/* now we are aligned with 8 bytes.
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* Use .Llong loop if left cmp bytes are equal or greater than 32B.
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*/
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cmpdi cr6,r5,31
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bgt cr6,.Llong
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.Lcmp_lt32bytes:
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/* compare 1 ~ 31 bytes, at least r3 addr is 8 bytes aligned now */
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cmpdi cr5,r5,7
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srdi r0,r5,3
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ble cr5,.Lcmp_rest_lt8bytes
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/* handle 8 ~ 31 bytes */
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clrldi r5,r5,61
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mtctr r0
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2:
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LD rA,0,r3
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LD rB,0,r4
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cmpld cr0,rA,rB
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addi r3,r3,8
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addi r4,r4,8
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bne cr0,.LcmpAB_lightweight
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bdnz 2b
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cmpwi r5,0
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beq .Lzero
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.Lcmp_rest_lt8bytes:
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/*
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* Here we have less than 8 bytes to compare. At least s1 is aligned to
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* 8 bytes, but s2 may not be. We must make sure s2 + 7 doesn't cross a
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* page boundary, otherwise we might read past the end of the buffer and
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* trigger a page fault. We use 4K as the conservative minimum page
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* size. If we detect that case we go to the byte-by-byte loop.
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*
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* Otherwise the next double word is loaded from s1 and s2, and shifted
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* right to compare the appropriate bits.
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*/
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clrldi r6,r4,(64-12) // r6 = r4 & 0xfff
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cmpdi r6,0xff8
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bgt .Lshort
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subfic r6,r5,8
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slwi r6,r6,3
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LD rA,0,r3
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LD rB,0,r4
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srd rA,rA,r6
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srd rB,rB,r6
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cmpld cr0,rA,rB
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bne cr0,.LcmpAB_lightweight
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b .Lzero
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.Lnon_zero:
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mr r3,rC
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blr
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.Llong:
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#ifdef CONFIG_ALTIVEC
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BEGIN_FTR_SECTION
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/* Try to use vmx loop if length is equal or greater than 4K */
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cmpldi cr6,r5,VMX_THRESH
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bge cr6,.Lsameoffset_vmx_cmp
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END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
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.Llong_novmx_cmp:
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#endif
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/* At least s1 addr is aligned with 8 bytes */
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li off8,8
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li off16,16
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li off24,24
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std r31,-8(r1)
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std r30,-16(r1)
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std r29,-24(r1)
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std r28,-32(r1)
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std r27,-40(r1)
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srdi r0,r5,5
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mtctr r0
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andi. r5,r5,31
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LD rA,0,r3
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LD rB,0,r4
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LD rC,off8,r3
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LD rD,off8,r4
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LD rE,off16,r3
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LD rF,off16,r4
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LD rG,off24,r3
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LD rH,off24,r4
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cmpld cr0,rA,rB
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addi r3,r3,32
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addi r4,r4,32
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bdz .Lfirst32
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LD rA,0,r3
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LD rB,0,r4
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cmpld cr1,rC,rD
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LD rC,off8,r3
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LD rD,off8,r4
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cmpld cr6,rE,rF
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LD rE,off16,r3
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LD rF,off16,r4
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cmpld cr7,rG,rH
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bne cr0,.LcmpAB
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LD rG,off24,r3
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LD rH,off24,r4
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cmpld cr0,rA,rB
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bne cr1,.LcmpCD
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addi r3,r3,32
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addi r4,r4,32
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bdz .Lsecond32
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.balign 16
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1: LD rA,0,r3
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LD rB,0,r4
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cmpld cr1,rC,rD
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bne cr6,.LcmpEF
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LD rC,off8,r3
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LD rD,off8,r4
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cmpld cr6,rE,rF
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bne cr7,.LcmpGH
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LD rE,off16,r3
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LD rF,off16,r4
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cmpld cr7,rG,rH
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bne cr0,.LcmpAB
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LD rG,off24,r3
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LD rH,off24,r4
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cmpld cr0,rA,rB
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bne cr1,.LcmpCD
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addi r3,r3,32
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addi r4,r4,32
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bdnz 1b
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.Lsecond32:
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cmpld cr1,rC,rD
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bne cr6,.LcmpEF
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cmpld cr6,rE,rF
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bne cr7,.LcmpGH
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cmpld cr7,rG,rH
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bne cr0,.LcmpAB
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bne cr1,.LcmpCD
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bne cr6,.LcmpEF
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bne cr7,.LcmpGH
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.Ltail:
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ld r31,-8(r1)
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ld r30,-16(r1)
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ld r29,-24(r1)
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ld r28,-32(r1)
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ld r27,-40(r1)
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cmpdi r5,0
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beq .Lzero
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b .Lshort
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.Lfirst32:
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cmpld cr1,rC,rD
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cmpld cr6,rE,rF
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cmpld cr7,rG,rH
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bne cr0,.LcmpAB
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bne cr1,.LcmpCD
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bne cr6,.LcmpEF
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bne cr7,.LcmpGH
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b .Ltail
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.LcmpAB:
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li r3,1
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bgt cr0,.Lout
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li r3,-1
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b .Lout
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.LcmpCD:
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li r3,1
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bgt cr1,.Lout
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li r3,-1
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b .Lout
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.LcmpEF:
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li r3,1
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bgt cr6,.Lout
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li r3,-1
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b .Lout
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.LcmpGH:
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li r3,1
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bgt cr7,.Lout
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li r3,-1
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.Lout:
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ld r31,-8(r1)
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ld r30,-16(r1)
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ld r29,-24(r1)
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ld r28,-32(r1)
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ld r27,-40(r1)
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blr
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.LcmpAB_lightweight: /* skip NV GPRS restore */
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li r3,1
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bgtlr
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li r3,-1
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blr
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#ifdef CONFIG_ALTIVEC
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.Lsameoffset_vmx_cmp:
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/* Enter with src/dst addrs has the same offset with 8 bytes
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* align boundary.
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*
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* There is an optimization based on following fact: memcmp()
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* prones to fail early at the first 32 bytes.
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* Before applying VMX instructions which will lead to 32x128bits
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* VMX regs load/restore penalty, we compare the first 32 bytes
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* so that we can catch the ~80% fail cases.
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*/
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li r0,4
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mtctr r0
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.Lsameoffset_prechk_32B_loop:
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LD rA,0,r3
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LD rB,0,r4
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cmpld cr0,rA,rB
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addi r3,r3,8
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addi r4,r4,8
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bne cr0,.LcmpAB_lightweight
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addi r5,r5,-8
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bdnz .Lsameoffset_prechk_32B_loop
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ENTER_VMX_OPS
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beq cr1,.Llong_novmx_cmp
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|
|
3:
|
|
/* need to check whether r4 has the same offset with r3
|
|
* for 16 bytes boundary.
|
|
*/
|
|
xor r0,r3,r4
|
|
andi. r0,r0,0xf
|
|
bne .Ldiffoffset_vmx_cmp_start
|
|
|
|
/* len is no less than 4KB. Need to align with 16 bytes further.
|
|
*/
|
|
andi. rA,r3,8
|
|
LD rA,0,r3
|
|
beq 4f
|
|
LD rB,0,r4
|
|
cmpld cr0,rA,rB
|
|
addi r3,r3,8
|
|
addi r4,r4,8
|
|
addi r5,r5,-8
|
|
|
|
beq cr0,4f
|
|
/* save and restore cr0 */
|
|
mfocrf r5,128
|
|
EXIT_VMX_OPS
|
|
mtocrf 128,r5
|
|
b .LcmpAB_lightweight
|
|
|
|
4:
|
|
/* compare 32 bytes for each loop */
|
|
srdi r0,r5,5
|
|
mtctr r0
|
|
clrldi r5,r5,59
|
|
li off16,16
|
|
|
|
.balign 16
|
|
5:
|
|
lvx v0,0,r3
|
|
lvx v1,0,r4
|
|
VCMPEQUD_RC(v0,v0,v1)
|
|
bnl cr6,7f
|
|
lvx v0,off16,r3
|
|
lvx v1,off16,r4
|
|
VCMPEQUD_RC(v0,v0,v1)
|
|
bnl cr6,6f
|
|
addi r3,r3,32
|
|
addi r4,r4,32
|
|
bdnz 5b
|
|
|
|
EXIT_VMX_OPS
|
|
cmpdi r5,0
|
|
beq .Lzero
|
|
b .Lcmp_lt32bytes
|
|
|
|
6:
|
|
addi r3,r3,16
|
|
addi r4,r4,16
|
|
|
|
7:
|
|
/* diff the last 16 bytes */
|
|
EXIT_VMX_OPS
|
|
LD rA,0,r3
|
|
LD rB,0,r4
|
|
cmpld cr0,rA,rB
|
|
li off8,8
|
|
bne cr0,.LcmpAB_lightweight
|
|
|
|
LD rA,off8,r3
|
|
LD rB,off8,r4
|
|
cmpld cr0,rA,rB
|
|
bne cr0,.LcmpAB_lightweight
|
|
b .Lzero
|
|
#endif
|
|
|
|
.Ldiffoffset_8bytes_make_align_start:
|
|
/* now try to align s1 with 8 bytes */
|
|
rlwinm r6,r3,3,26,28
|
|
beq .Ldiffoffset_align_s1_8bytes
|
|
|
|
clrrdi r3,r3,3
|
|
LD rA,0,r3
|
|
LD rB,0,r4 /* unaligned load */
|
|
sld rA,rA,r6
|
|
srd rA,rA,r6
|
|
srd rB,rB,r6
|
|
cmpld cr0,rA,rB
|
|
srwi r6,r6,3
|
|
bne cr0,.LcmpAB_lightweight
|
|
|
|
subfic r6,r6,8
|
|
subf. r5,r6,r5
|
|
addi r3,r3,8
|
|
add r4,r4,r6
|
|
|
|
beq .Lzero
|
|
|
|
.Ldiffoffset_align_s1_8bytes:
|
|
/* now s1 is aligned with 8 bytes. */
|
|
#ifdef CONFIG_ALTIVEC
|
|
BEGIN_FTR_SECTION
|
|
/* only do vmx ops when the size equal or greater than 4K bytes */
|
|
cmpdi cr5,r5,VMX_THRESH
|
|
bge cr5,.Ldiffoffset_vmx_cmp
|
|
END_FTR_SECTION_IFSET(CPU_FTR_ARCH_207S)
|
|
|
|
.Ldiffoffset_novmx_cmp:
|
|
#endif
|
|
|
|
|
|
cmpdi cr5,r5,31
|
|
ble cr5,.Lcmp_lt32bytes
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
b .Llong_novmx_cmp
|
|
#else
|
|
b .Llong
|
|
#endif
|
|
|
|
#ifdef CONFIG_ALTIVEC
|
|
.Ldiffoffset_vmx_cmp:
|
|
/* perform a 32 bytes pre-checking before
|
|
* enable VMX operations.
|
|
*/
|
|
li r0,4
|
|
mtctr r0
|
|
.Ldiffoffset_prechk_32B_loop:
|
|
LD rA,0,r3
|
|
LD rB,0,r4
|
|
cmpld cr0,rA,rB
|
|
addi r3,r3,8
|
|
addi r4,r4,8
|
|
bne cr0,.LcmpAB_lightweight
|
|
addi r5,r5,-8
|
|
bdnz .Ldiffoffset_prechk_32B_loop
|
|
|
|
ENTER_VMX_OPS
|
|
beq cr1,.Ldiffoffset_novmx_cmp
|
|
|
|
.Ldiffoffset_vmx_cmp_start:
|
|
/* Firstly try to align r3 with 16 bytes */
|
|
andi. r6,r3,0xf
|
|
li off16,16
|
|
beq .Ldiffoffset_vmx_s1_16bytes_align
|
|
|
|
LVS v3,0,r3
|
|
LVS v4,0,r4
|
|
|
|
lvx v5,0,r3
|
|
lvx v6,0,r4
|
|
LD_VSR_CROSS16B(r3,v3,v5,v7,v9)
|
|
LD_VSR_CROSS16B(r4,v4,v6,v8,v10)
|
|
|
|
VCMPEQUB_RC(v7,v9,v10)
|
|
bnl cr6,.Ldiffoffset_vmx_diff_found
|
|
|
|
subfic r6,r6,16
|
|
subf r5,r6,r5
|
|
add r3,r3,r6
|
|
add r4,r4,r6
|
|
|
|
.Ldiffoffset_vmx_s1_16bytes_align:
|
|
/* now s1 is aligned with 16 bytes */
|
|
lvx v6,0,r4
|
|
LVS v4,0,r4
|
|
srdi r6,r5,5 /* loop for 32 bytes each */
|
|
clrldi r5,r5,59
|
|
mtctr r6
|
|
|
|
.balign 16
|
|
.Ldiffoffset_vmx_32bytesloop:
|
|
/* the first qw of r4 was saved in v6 */
|
|
lvx v9,0,r3
|
|
LD_VSR_CROSS16B(r4,v4,v6,v8,v10)
|
|
VCMPEQUB_RC(v7,v9,v10)
|
|
vor v6,v8,v8
|
|
bnl cr6,.Ldiffoffset_vmx_diff_found
|
|
|
|
addi r3,r3,16
|
|
addi r4,r4,16
|
|
|
|
lvx v9,0,r3
|
|
LD_VSR_CROSS16B(r4,v4,v6,v8,v10)
|
|
VCMPEQUB_RC(v7,v9,v10)
|
|
vor v6,v8,v8
|
|
bnl cr6,.Ldiffoffset_vmx_diff_found
|
|
|
|
addi r3,r3,16
|
|
addi r4,r4,16
|
|
|
|
bdnz .Ldiffoffset_vmx_32bytesloop
|
|
|
|
EXIT_VMX_OPS
|
|
|
|
cmpdi r5,0
|
|
beq .Lzero
|
|
b .Lcmp_lt32bytes
|
|
|
|
.Ldiffoffset_vmx_diff_found:
|
|
EXIT_VMX_OPS
|
|
/* anyway, the diff will appear in next 16 bytes */
|
|
li r5,16
|
|
b .Lcmp_lt32bytes
|
|
|
|
#endif
|
|
EXPORT_SYMBOL(memcmp)
|