mirror of
https://github.com/AuxXxilium/linux_dsm_epyc7002.git
synced 2024-12-16 12:56:54 +07:00
d74c67dd78
The crtc_h/vdisplay fields may not match the CRTC viewport dimensions
with special modes such as interlaced ones.
Fixes the HW cursor disappearing in the bottom half of the screen with
interlaced modes.
Fixes: 6b16cf7785
("drm/radeon: Hide the HW cursor while it's out of bounds")
Cc: stable@vger.kernel.org
Reported-by: Ashutosh Kumar <ashutosh.kumar@amd.com>
Tested-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
385 lines
11 KiB
C
385 lines
11 KiB
C
/*
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* Copyright 2007-8 Advanced Micro Devices, Inc.
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* Copyright 2008 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: Dave Airlie
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* Alex Deucher
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*/
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#include <drm/drmP.h>
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#include <drm/radeon_drm.h>
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#include "radeon.h"
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static void radeon_lock_cursor(struct drm_crtc *crtc, bool lock)
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{
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struct radeon_device *rdev = crtc->dev->dev_private;
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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uint32_t cur_lock;
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if (ASIC_IS_DCE4(rdev)) {
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cur_lock = RREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= EVERGREEN_CURSOR_UPDATE_LOCK;
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else
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cur_lock &= ~EVERGREEN_CURSOR_UPDATE_LOCK;
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WREG32(EVERGREEN_CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
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} else if (ASIC_IS_AVIVO(rdev)) {
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cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK;
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else
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cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK;
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WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock);
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} else {
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cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset);
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if (lock)
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cur_lock |= RADEON_CUR_LOCK;
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else
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cur_lock &= ~RADEON_CUR_LOCK;
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock);
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}
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}
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static void radeon_hide_cursor(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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if (ASIC_IS_DCE4(rdev)) {
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WREG32_IDX(EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset,
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EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
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EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32_IDX(AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset,
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(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
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} else {
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u32 reg;
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switch (radeon_crtc->crtc_id) {
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case 0:
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reg = RADEON_CRTC_GEN_CNTL;
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break;
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case 1:
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reg = RADEON_CRTC2_GEN_CNTL;
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break;
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default:
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return;
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}
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WREG32_IDX(reg, RREG32_IDX(reg) & ~RADEON_CRTC_CUR_EN);
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}
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}
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static void radeon_show_cursor(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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if (radeon_crtc->cursor_out_of_bounds)
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return;
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(EVERGREEN_CUR_SURFACE_ADDRESS_HIGH + radeon_crtc->crtc_offset,
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upper_32_bits(radeon_crtc->cursor_addr));
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WREG32(EVERGREEN_CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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lower_32_bits(radeon_crtc->cursor_addr));
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WREG32(RADEON_MM_INDEX, EVERGREEN_CUR_CONTROL + radeon_crtc->crtc_offset);
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WREG32(RADEON_MM_DATA, EVERGREEN_CURSOR_EN |
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EVERGREEN_CURSOR_MODE(EVERGREEN_CURSOR_24_8_PRE_MULT) |
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EVERGREEN_CURSOR_URGENT_CONTROL(EVERGREEN_CURSOR_URGENT_1_2));
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} else if (ASIC_IS_AVIVO(rdev)) {
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if (rdev->family >= CHIP_RV770) {
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if (radeon_crtc->crtc_id)
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WREG32(R700_D2CUR_SURFACE_ADDRESS_HIGH,
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upper_32_bits(radeon_crtc->cursor_addr));
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else
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WREG32(R700_D1CUR_SURFACE_ADDRESS_HIGH,
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upper_32_bits(radeon_crtc->cursor_addr));
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}
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WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset,
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lower_32_bits(radeon_crtc->cursor_addr));
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WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset);
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WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN |
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(AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT));
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} else {
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
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radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr);
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switch (radeon_crtc->crtc_id) {
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case 0:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL);
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break;
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case 1:
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WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL);
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break;
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default:
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return;
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}
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WREG32_P(RADEON_MM_DATA, (RADEON_CRTC_CUR_EN |
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(RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)),
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~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK));
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}
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}
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static int radeon_cursor_move_locked(struct drm_crtc *crtc, int x, int y)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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int xorigin = 0, yorigin = 0;
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int w = radeon_crtc->cursor_width;
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radeon_crtc->cursor_x = x;
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radeon_crtc->cursor_y = y;
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if (ASIC_IS_AVIVO(rdev)) {
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/* avivo cursor are offset into the total surface */
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x += crtc->x;
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y += crtc->y;
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}
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if (x < 0)
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xorigin = min(-x, radeon_crtc->max_cursor_width - 1);
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if (y < 0)
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yorigin = min(-y, radeon_crtc->max_cursor_height - 1);
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if (!ASIC_IS_AVIVO(rdev)) {
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x += crtc->x;
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y += crtc->y;
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}
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DRM_DEBUG("x %d y %d c->x %d c->y %d\n", x, y, crtc->x, crtc->y);
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/* fixed on DCE6 and newer */
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if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE6(rdev)) {
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int i = 0;
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struct drm_crtc *crtc_p;
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/*
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* avivo cursor image can't end on 128 pixel boundary or
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* go past the end of the frame if both crtcs are enabled
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*
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* NOTE: It is safe to access crtc->enabled of other crtcs
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* without holding either the mode_config lock or the other
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* crtc's lock as long as write access to this flag _always_
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* grabs all locks.
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*/
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list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) {
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if (crtc_p->enabled)
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i++;
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}
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if (i > 1) {
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int cursor_end, frame_end;
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cursor_end = x + w;
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frame_end = crtc->x + crtc->mode.crtc_hdisplay;
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if (cursor_end >= frame_end) {
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w = w - (cursor_end - frame_end);
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if (!(frame_end & 0x7f))
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w--;
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} else if (cursor_end <= 0) {
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goto out_of_bounds;
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} else if (!(cursor_end & 0x7f)) {
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w--;
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}
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if (w <= 0) {
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goto out_of_bounds;
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}
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}
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}
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if (x <= (crtc->x - w) || y <= (crtc->y - radeon_crtc->cursor_height) ||
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x >= (crtc->x + crtc->mode.hdisplay) ||
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y >= (crtc->y + crtc->mode.vdisplay))
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goto out_of_bounds;
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x += xorigin;
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y += yorigin;
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if (ASIC_IS_DCE4(rdev)) {
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WREG32(EVERGREEN_CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(EVERGREEN_CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(EVERGREEN_CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else if (ASIC_IS_AVIVO(rdev)) {
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WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, (x << 16) | y);
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WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, (xorigin << 16) | yorigin);
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WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset,
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((w - 1) << 16) | (radeon_crtc->cursor_height - 1));
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} else {
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x -= crtc->x;
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y -= crtc->y;
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if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)
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y *= 2;
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WREG32(RADEON_CUR_HORZ_VERT_OFF + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (xorigin << 16)
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| yorigin));
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WREG32(RADEON_CUR_HORZ_VERT_POSN + radeon_crtc->crtc_offset,
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(RADEON_CUR_LOCK
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| (x << 16)
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| y));
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/* offset is from DISP(2)_BASE_ADDRESS */
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WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset,
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radeon_crtc->cursor_addr - radeon_crtc->legacy_display_base_addr +
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yorigin * 256);
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}
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if (radeon_crtc->cursor_out_of_bounds) {
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radeon_crtc->cursor_out_of_bounds = false;
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if (radeon_crtc->cursor_bo)
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radeon_show_cursor(crtc);
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}
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return 0;
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out_of_bounds:
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if (!radeon_crtc->cursor_out_of_bounds) {
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radeon_hide_cursor(crtc);
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radeon_crtc->cursor_out_of_bounds = true;
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}
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return 0;
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}
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int radeon_crtc_cursor_move(struct drm_crtc *crtc,
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int x, int y)
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{
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int ret;
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radeon_lock_cursor(crtc, true);
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ret = radeon_cursor_move_locked(crtc, x, y);
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radeon_lock_cursor(crtc, false);
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return ret;
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}
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int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
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struct drm_file *file_priv,
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uint32_t handle,
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uint32_t width,
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uint32_t height,
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int32_t hot_x,
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int32_t hot_y)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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struct radeon_device *rdev = crtc->dev->dev_private;
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struct drm_gem_object *obj;
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struct radeon_bo *robj;
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int ret;
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if (!handle) {
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/* turn off cursor */
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radeon_hide_cursor(crtc);
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obj = NULL;
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goto unpin;
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}
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if ((width > radeon_crtc->max_cursor_width) ||
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(height > radeon_crtc->max_cursor_height)) {
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DRM_ERROR("bad cursor width or height %d x %d\n", width, height);
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return -EINVAL;
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}
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obj = drm_gem_object_lookup(file_priv, handle);
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if (!obj) {
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DRM_ERROR("Cannot find cursor object %x for crtc %d\n", handle, radeon_crtc->crtc_id);
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return -ENOENT;
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}
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robj = gem_to_radeon_bo(obj);
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ret = radeon_bo_reserve(robj, false);
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if (ret != 0) {
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drm_gem_object_unreference_unlocked(obj);
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return ret;
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}
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/* Only 27 bit offset for legacy cursor */
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ret = radeon_bo_pin_restricted(robj, RADEON_GEM_DOMAIN_VRAM,
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ASIC_IS_AVIVO(rdev) ? 0 : 1 << 27,
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&radeon_crtc->cursor_addr);
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radeon_bo_unreserve(robj);
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if (ret) {
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DRM_ERROR("Failed to pin new cursor BO (%d)\n", ret);
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drm_gem_object_unreference_unlocked(obj);
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return ret;
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}
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radeon_lock_cursor(crtc, true);
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if (width != radeon_crtc->cursor_width ||
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height != radeon_crtc->cursor_height ||
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hot_x != radeon_crtc->cursor_hot_x ||
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hot_y != radeon_crtc->cursor_hot_y) {
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int x, y;
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x = radeon_crtc->cursor_x + radeon_crtc->cursor_hot_x - hot_x;
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y = radeon_crtc->cursor_y + radeon_crtc->cursor_hot_y - hot_y;
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radeon_crtc->cursor_width = width;
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radeon_crtc->cursor_height = height;
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radeon_crtc->cursor_hot_x = hot_x;
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radeon_crtc->cursor_hot_y = hot_y;
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radeon_cursor_move_locked(crtc, x, y);
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}
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radeon_show_cursor(crtc);
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radeon_lock_cursor(crtc, false);
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unpin:
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if (radeon_crtc->cursor_bo) {
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struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
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ret = radeon_bo_reserve(robj, false);
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if (likely(ret == 0)) {
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radeon_bo_unpin(robj);
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radeon_bo_unreserve(robj);
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}
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drm_gem_object_unreference_unlocked(radeon_crtc->cursor_bo);
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}
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radeon_crtc->cursor_bo = obj;
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return 0;
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}
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/**
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* radeon_cursor_reset - Re-set the current cursor, if any.
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*
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* @crtc: drm crtc
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*
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* If the CRTC passed in currently has a cursor assigned, this function
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* makes sure it's visible.
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*/
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void radeon_cursor_reset(struct drm_crtc *crtc)
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{
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struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
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if (radeon_crtc->cursor_bo) {
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radeon_lock_cursor(crtc, true);
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radeon_cursor_move_locked(crtc, radeon_crtc->cursor_x,
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radeon_crtc->cursor_y);
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radeon_show_cursor(crtc);
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radeon_lock_cursor(crtc, false);
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}
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}
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