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https://github.com/AuxXxilium/linux_dsm_epyc7002.git
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c80dfd9bf5
Add CRG driver for Hi3516CV300 SoC. CRG(Clock and Reset Generator) module generates clock and reset signals used by other module blocks on SoC. Signed-off-by: Pan Wen <wenpan@hisilicon.com> Signed-off-by: Jiancheng Xue <xuejiancheng@hisilicon.com> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
16 lines
522 B
Makefile
16 lines
522 B
Makefile
#
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# Hisilicon Clock specific Makefile
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#
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obj-y += clk.o clkgate-separated.o clkdivider-hi6220.o
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obj-$(CONFIG_ARCH_HI3xxx) += clk-hi3620.o
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obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
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obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
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obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
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obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
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obj-$(CONFIG_COMMON_CLK_HI3798CV200) += crg-hi3798cv200.o
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obj-$(CONFIG_COMMON_CLK_HI6220) += clk-hi6220.o
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obj-$(CONFIG_RESET_HISI) += reset.o
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obj-$(CONFIG_STUB_CLK_HI6220) += clk-hi6220-stub.o
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